| /freebsd/contrib/llvm-project/llvm/utils/TableGen/Common/ |
| H A D | InfoByHwMode.h | 39 DefaultMode = CodeGenHwModes::DefaultMode, enumerator
50 if (AI != A.end() && AI->first == DefaultMode) { in union_modes()
54 if (BI != B.end() && BI->first == DefaultMode) { in union_modes()
84 Modes.push_back(DefaultMode); in union_modes()
111 return !Map.empty() && Map.begin()->first == DefaultMode; in hasDefault()
130 assert(F != Map.end() && F->first == DefaultMode); in get()
136 return Map.size() == 1 && Map.begin()->first == DefaultMode; in isSimple()
147 Map.insert(std::pair(DefaultMode, I)); in makeSimple()
157 ValueTypeByHwMode(MVT T) { Map.insert({DefaultMode, T}); } in ValueTypeByHwMode()
231 SubRegRangeByHwMode(SubRegRange Range) { Map.insert({DefaultMode, Range}); } in SubRegRangeByHwMode()
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| H A D | CodeGenHwModes.h | 46 enum : unsigned { DefaultMode = 0 }; enumerator
56 if (IncludeDefault && Id == CodeGenHwModes::DefaultMode)
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| H A D | CodeGenRegisters.h | 123 if (M == DefaultMode) in addComposite()
137 SubRegRange &Range = this->Range.get(DefaultMode); in addComposite()
138 SubRegRange &ARange = A->Range.get(DefaultMode); in addComposite()
139 SubRegRange &BRange = B->Range.get(DefaultMode); in addComposite()
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| H A D | InfoByHwMode.cpp | 26 if (Mode == DefaultMode) in getModeName()
71 if (D != Map.end() && D->first == DefaultMode) in getOrCreateTypeForMode()
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| H A D | CodeGenHwModes.cpp | 88 return DefaultMode; in getHwModeId()
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| H A D | CodeGenDAGPatterns.cpp | 125 if (DefaultMode == M) { in insert()
147 if (M == DefaultMode || hasMode(M)) in constrain()
149 Map.insert({M, Map.at(DefaultMode)}); in constrain()
856 TypeSetByHwMode::SetType &LegalTypes = LegalCache.getOrCreate(DefaultMode); in getLegalTypes()
1792 if (S.get(DefaultMode).empty()) in setDefaultMode()
4460 if (M == DefaultMode) in ExpandHwModeBasedTypes()
4475 bool HasDefault = Modes.count(DefaultMode); in ExpandHwModeBasedTypes()
4477 AppendPattern(P, DefaultMode, DefaultCheck); in ExpandHwModeBasedTypes()
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| H A D | CodeGenRegisters.cpp | 62 Range.insertSubRegRangeForMode(DefaultMode, SubRegRange(R)); in CodeGenSubRegIndex()
819 RSI.insertRegSizeForMode(DefaultMode, RI); in CodeGenRegisterClass()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.td | 474 def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
476 def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
478 def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
480 def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
482 def VecF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
484 def VecF32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
487 def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
489 def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
491 def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
493 def VecPF16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode],
[all …]
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| /freebsd/contrib/llvm-project/llvm/utils/TableGen/ |
| H A D | CodeEmitterGen.cpp | 71 CodeGenTarget &Target, unsigned HwMode = DefaultMode);
303 if (ModeId == DefaultMode) { in getInstructionCases()
305 " case " + itostr(DefaultMode) + ": InstBitsByHw = InstBits"; in getInstructionCases()
399 if (HwMode == DefaultMode) in emitInstructionBaseValues()
525 emitInstructionBaseValues(o, NumberedInstructions, Target, DefaultMode); in run()
529 if (HwMode == DefaultMode) in run()
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| H A D | RegisterBankEmitter.cpp | 268 if (M == DefaultMode) in emitBaseClassImplementation()
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| H A D | DecoderEmitter.cpp | 2444 if (P.first == DefaultMode) { in collectHwModesReferencedForEncodings()
2455 if (M == DefaultMode) in collectHwModesReferencedForEncodings()
2537 if (ModeId == DefaultMode) { in run()
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| H A D | SubtargetEmitter.cpp | 1810 if (P.first == DefaultMode) in EmitHwModeCheck()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIModeRegister.cpp | 122 unsigned DefaultMode = FP_ROUND_ROUND_TO_NEAREST; member in __anon61d306190111::SIModeRegister
124 Status(FP_ROUND_MODE_DP(0x3), FP_ROUND_MODE_DP(DefaultMode));
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArch.td | 32 defvar LA32 = DefaultMode;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVFeatures.td | 1290 defvar RV32 = DefaultMode;
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Target/ |
| H A D | Target.td | 39 def DefaultMode : HwMode<"", []>;
102 // If the HwModes provided for SubRegRanges does not include the DefaultMode,
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