| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | LiveRangeShrink.cpp | 168 const MachineOperand *DefMO = nullptr; in runOnMachineFunction()
189 if (DefMO) { in runOnMachineFunction()
193 DefMO = &MO; in runOnMachineFunction()
194 } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO && in runOnMachineFunction()
195 MRI.getRegClass(DefMO->getReg()) == in runOnMachineFunction()
220 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) { in runOnMachineFunction()
166 const MachineOperand *DefMO = nullptr; runOnMachineFunction() local
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| H A D | CodeGenCommonISel.cpp | 257 for (auto *DefMO : DbgUsers) { in salvageDebugInfoForDbgValue() local
258 MachineInstr *DbgMI = DefMO->getParent(); in salvageDebugInfoForDbgValue()
264 DbgMI->findRegisterUseOperandIdx(DefMO->getReg(), /*TRI=*/nullptr); in salvageDebugInfoForDbgValue()
265 assert(UseMOIdx != -1 && DbgMI->hasDebugOperandForReg(DefMO->getReg()) && in salvageDebugInfoForDbgValue()
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| H A D | InitUndef.cpp | 101 return llvm::any_of(MI.defs(), [](const MachineOperand &DefMO) { in isEarlyClobberMI() argument
102 return DefMO.isReg() && DefMO.isEarlyClobber(); in isEarlyClobberMI()
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| H A D | FixupStatepointCallerSaved.cpp | 486 MachineOperand &DefMO = MI.getOperand(I); in rewriteStatepoint() local
487 assert(DefMO.isReg() && DefMO.isDef() && "Expected Reg Def operand"); in rewriteStatepoint()
488 Register Reg = DefMO.getReg(); in rewriteStatepoint()
489 assert(DefMO.isTied() && "Def is expected to be tied"); in rewriteStatepoint()
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| H A D | ModuloSchedule.cpp | 1623 for (MachineOperand &DefMO : MI->defs()) { in filterInstructions()
1625 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in filterInstructions()
1634 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in filterInstructions()
1938 for (MachineOperand &DefMO : MI->defs()) { in rewriteUsesOf()
1940 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in rewriteUsesOf()
1949 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in rewriteUsesOf()
2420 for (MachineOperand &DefMO : OrigMI->defs()) { in generatePhi()
2421 if (!DefMO.isReg() || DefMO.isDead()) in generatePhi()
2423 Register OrigReg = DefMO.getReg(); in generatePhi()
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| H A D | MachineFunction.cpp | 1205 for (const auto &DefMO : DefMI.operands()) { in finalizeDebugInstrRefs() local
1206 if (DefMO.isReg() && DefMO.isDef() && DefMO.getReg() == Reg) in finalizeDebugInstrRefs()
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| H A D | MachineLICM.cpp | 1194 MachineOperand &DefMO = MI.getOperand(i); in IsCheapInstruction() local
1195 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
1198 Register Reg = DefMO.getReg(); in IsCheapInstruction()
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| H A D | ScheduleDAGInstrs.cpp | 318 MachineOperand &DefMO = DefInstr->getOperand(I->OpIdx); in addPhysRegDeps() local
320 (Kind != SDep::Output || !MO.isDead() || !DefMO.isDead())) { in addPhysRegDeps()
321 SDep Dep(SU, Kind, DefMO.getReg()); in addPhysRegDeps()
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| H A D | MachineInstr.cpp | 1163 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands() local
1165 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands()
1167 assert(!DefMO.isTied() && "Def is already tied to another use"); in tieOperands()
1183 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); in tieOperands()
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| H A D | RegisterCoalescer.cpp | 1384 MachineOperand &DefMO = NewMI.getOperand(0); in reMaterializeTrivialDef() local
1385 if (DefMO.getSubReg() == DstIdx) { in reMaterializeTrivialDef()
1405 DefMO.setIsUndef(false); // Only subregs can have def+undef. in reMaterializeTrivialDef()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | TileShapeInfo.h | 72 for (const MachineOperand &DefMO : MRI->def_operands(Reg)) { in deduceImm()
73 const auto *MI = DefMO.getParent(); in deduceImm() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyExplicitLocals.cpp | 209 for (MachineOperand &DefMO : Def->explicit_uses()) { in findStartOfTree()
210 if (!DefMO.isReg()) in findStartOfTree()
212 return findStartOfTree(DefMO, MRI, MFI); in findStartOfTree()
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| H A D | WebAssemblyRegStackify.cpp | 651 MachineOperand &DefMO = Def->getOperand(0); in moveAndTeeForMultiUse() local
655 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIPeepholeSDWA.cpp | 303 for (auto &DefMO : DefInstr->defs()) { in findSingleRegDef() local
304 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
305 return &DefMO; in findSingleRegDef()
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| H A D | SIInsertWaitcnts.cpp | 887 MachineOperand &DefMO = Inst.getOperand(I); in updateByEvent() local
888 if (DefMO.isReg() && DefMO.isDef() && in updateByEvent()
889 TRI->isVGPR(*MRI, DefMO.getReg())) { in updateByEvent()
891 TRI->getEncodingValue(AMDGPU::getMCReg(DefMO.getReg(), *ST)), in updateByEvent()
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| H A D | SIInstrInfo.h | 1065 const MachineOperand &DefMO) const { in isInlineConstant() argument
1071 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]); in isInlineConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.cpp | 4333 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4335 if (DefMO.isReg() && DefMO.getReg().isPhysical()) { in getOperandLatency()
4336 if (DefMO.isImplicit()) { in getOperandLatency()
4337 for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) { in getOperandLatency()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 457 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
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| H A D | ARMBaseInstrInfo.cpp | 4370 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4371 Register Reg = DefMO.getReg(); in getOperandLatency()
4393 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO, in getOperandLatency()
4400 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, in getOperandLatencyImpl() argument
4428 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit()) in getOperandLatencyImpl()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 177 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
178 Register Reg = DefMO.getReg(); in getOperandLatency()
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