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Searched refs:DefMO (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeShrink.cpp185 const MachineOperand *DefMO = nullptr; in runOnMachineFunction() local
206 if (DefMO) { in runOnMachineFunction()
210 DefMO = &MO; in runOnMachineFunction()
211 } else if (MRI.hasOneNonDBGUse(Reg) && MRI.hasOneDef(Reg) && DefMO && in runOnMachineFunction()
212 MRI.getRegClass(DefMO->getReg()) == in runOnMachineFunction()
237 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) { in runOnMachineFunction()
H A DCodeGenCommonISel.cpp265 for (auto *DefMO : DbgUsers) { in salvageDebugInfoForDbgValue() local
266 MachineInstr *DbgMI = DefMO->getParent(); in salvageDebugInfoForDbgValue()
272 DbgMI->findRegisterUseOperandIdx(DefMO->getReg(), /*TRI=*/nullptr); in salvageDebugInfoForDbgValue()
273 assert(UseMOIdx != -1 && DbgMI->hasDebugOperandForReg(DefMO->getReg()) && in salvageDebugInfoForDbgValue()
H A DInitUndef.cpp108 return llvm::any_of(MI.all_defs(), [](const MachineOperand &DefMO) { in isEarlyClobberMI() argument
109 return DefMO.isReg() && DefMO.isEarlyClobber(); in isEarlyClobberMI()
H A DFixupStatepointCallerSaved.cpp483 MachineOperand &DefMO = MI.getOperand(I); in rewriteStatepoint() local
484 assert(DefMO.isReg() && DefMO.isDef() && "Expected Reg Def operand"); in rewriteStatepoint()
485 Register Reg = DefMO.getReg(); in rewriteStatepoint()
486 assert(DefMO.isTied() && "Def is expected to be tied"); in rewriteStatepoint()
H A DMachineSink.cpp1755 MachineOperand &DefMO = I.getOperand(0); in aggressivelySinkIntoCycle() local
1756 for (MachineInstr &MI : MRI->use_instructions(DefMO.getReg())) { in aggressivelySinkIntoCycle()
1757 Uses.push_back({{DefMO.getReg(), DefMO.getSubReg()}, &MI}); in aggressivelySinkIntoCycle()
1800 if (DefMO.getReg().isVirtual()) { in aggressivelySinkIntoCycle()
1801 const TargetRegisterClass *TRC = MRI->getRegClass(DefMO.getReg()); in aggressivelySinkIntoCycle()
1803 NewMI->substituteRegister(DefMO.getReg(), DestReg, DefMO.getSubReg(), in aggressivelySinkIntoCycle()
H A DModuloSchedule.cpp1642 for (MachineOperand &DefMO : MI->defs()) { in filterInstructions()
1644 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in filterInstructions()
1653 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in filterInstructions()
1957 for (MachineOperand &DefMO : MI->defs()) { in rewriteUsesOf()
1959 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) { in rewriteUsesOf()
1968 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0, in rewriteUsesOf()
2447 for (MachineOperand &DefMO : OrigMI->defs()) { in generatePhi()
2448 if (!DefMO.isReg() || DefMO.isDead()) in generatePhi()
2450 Register OrigReg = DefMO.getReg(); in generatePhi()
H A DMachineTraceMetrics.cpp686 MachineOperand *DefMO = MRI->getOneDef(VirtReg); in DataDep() local
687 assert(DefMO && "Register does not have unique def"); in DataDep()
688 DefMI = DefMO->getParent(); in DataDep()
689 DefOp = DefMO->getOperandNo(); in DataDep()
H A DMachineFunction.cpp1260 for (const auto &DefMO : DefMI.operands()) { in finalizeDebugInstrRefs() local
1261 if (DefMO.isReg() && DefMO.isDef() && DefMO.getReg() == Reg) in finalizeDebugInstrRefs()
H A DMachineLICM.cpp1218 MachineOperand &DefMO = MI.getOperand(i); in IsCheapInstruction() local
1219 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction()
1222 Register Reg = DefMO.getReg(); in IsCheapInstruction()
H A DScheduleDAGInstrs.cpp339 MachineOperand &DefMO = DefInstr->getOperand(I->OpIdx); in addPhysRegDeps() local
341 (Kind != SDep::Output || !MO.isDead() || !DefMO.isDead())) { in addPhysRegDeps()
342 SDep Dep(SU, Kind, DefMO.getReg()); in addPhysRegDeps()
H A DMachineInstr.cpp1190 MachineOperand &DefMO = getOperand(DefIdx); in tieOperands() local
1192 assert(DefMO.isDef() && "DefIdx must be a def operand"); in tieOperands()
1194 assert(!DefMO.isTied() && "Def is already tied to another use"); in tieOperands()
1210 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); in tieOperands()
H A DRegisterCoalescer.cpp1418 MachineOperand &DefMO = NewMI.getOperand(0); in reMaterializeTrivialDef() local
1419 if (DefMO.getSubReg() == DstIdx) { in reMaterializeTrivialDef()
1439 DefMO.setIsUndef(false); // Only subregs can have def+undef. in reMaterializeTrivialDef()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTileShapeInfo.h120 for (const MachineOperand &DefMO : MRI->def_operands(Reg)) { in deduceImm() local
121 const auto *MI = DefMO.getParent(); in deduceImm()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyExplicitLocals.cpp209 for (MachineOperand &DefMO : Def->explicit_uses()) { in findStartOfTree()
210 if (!DefMO.isReg()) in findStartOfTree()
212 return findStartOfTree(DefMO, MRI, MFI); in findStartOfTree()
H A DWebAssemblyRegStackify.cpp680 MachineOperand &DefMO = Def->getOperand(0); in moveAndTeeForMultiUse() local
684 .addReg(DefReg, getUndefRegState(DefMO.isDead())); in moveAndTeeForMultiUse()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp320 for (auto &DefMO : DefInstr->defs()) { in findSingleRegDef() local
321 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg()) in findSingleRegDef()
322 return &DefMO; in findSingleRegDef()
H A DSIInstrInfo.h1116 const MachineOperand &DefMO) const { in isInlineConstant() argument
1122 return isInlineConstant(DefMO, MI.getDesc().operands()[OpIdx]); in isInlineConstant()
H A DSIInsertWaitcnts.cpp994 for (MachineOperand &DefMO : Inst.all_defs()) { in updateByEvent()
995 if (TRI->isVGPR(*MRI, DefMO.getReg())) { in updateByEvent()
996 setScoreByOperand(&Inst, TRI, MRI, DefMO, EXP_CNT, CurrScore); in updateByEvent()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVModuleAnalysis.cpp503 const MachineOperand &DefMO = MI.getOperand(0); in collectDeclarations() local
506 MAI.Reqs.addExtension(SPIRV::Extension::Extension(DefMO.getImm())); in collectDeclarations()
510 MAI.Reqs.addCapability(SPIRV::Capability::Capability(DefMO.getImm())); in collectDeclarations()
516 if (DefMO.isReg() && isDeclSection(MRI, MI) && in collectDeclarations()
517 !MAI.hasRegisterAlias(MF, DefMO.getReg())) in collectDeclarations()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp4337 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4339 if (DefMO.isReg() && DefMO.getReg().isPhysical()) { in getOperandLatency()
4340 if (DefMO.isImplicit()) { in getOperandLatency()
4341 for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) { in getOperandLatency()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h448 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
H A DARMBaseInstrInfo.cpp4213 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
4214 Register Reg = DefMO.getReg(); in getOperandLatency()
4236 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO, in getOperandLatency()
4243 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI, in getOperandLatencyImpl() argument
4271 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit()) in getOperandLatencyImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp175 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency() local
176 Register Reg = DefMO.getReg(); in getOperandLatency()