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Searched refs:DefMI (Results 1 – 25 of 92) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMLxExpansionPass.cpp94 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI() local
96 if (DefMI->getParent() != MBB) in getAccDefMI()
98 if (DefMI->isCopyLike()) { in getAccDefMI()
99 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
101 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
104 } else if (DefMI->isInsertSubreg()) { in getAccDefMI()
105 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
107 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
113 return DefMI; in getAccDefMI()
146 MachineInstr *DefMI = MRI->getVRegDef(Reg); in hasLoopHazard() local
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H A DARMHazardRecognizer.cpp26 static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, in hasRAWHazard() argument
37 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI); in hasRAWHazard()
52 MachineInstr *DefMI = LastMI; in getHazardType() local
65 DefMI = &*I; in getHazardType()
69 if (TII.isFpMLxInstruction(DefMI->getOpcode()) && in getHazardType()
71 hasRAWHazard(DefMI, MI, TII.getRegisterInfo()))) { in getHazardType()
H A DARMFixCortexA57AES1742098Pass.cpp361 MachineInstr *DefMI = *It; in analyzeMF() local
365 << printReg(MOp.getReg(), TRI) << ": " << *DefMI); in analyzeMF()
372 MachineBasicBlock::iterator DefIt = DefMI; in analyzeMF()
374 if (DefIt != DefMI->getParent()->end()) { in analyzeMF()
375 LLVM_DEBUG(dbgs() << "Moving Fixup to immediately after " << *DefMI in analyzeMF()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetSchedule.cpp171 const MachineInstr *DefMI, unsigned DefOperIdx, in computeOperandLatency() argument
174 const unsigned InstrLatency = computeInstrLatency(DefMI); in computeOperandLatency()
175 const unsigned DefaultDefLatency = TII->defaultDefLatency(SchedModel, *DefMI); in computeOperandLatency()
183 OperLatency = TII->getOperandLatency(&InstrItins, *DefMI, DefOperIdx, in computeOperandLatency()
187 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
198 const MCSchedClassDesc *SCDesc = resolveSchedClass(DefMI); in computeOperandLatency()
199 unsigned DefIdx = findDefIdx(DefMI, DefOperIdx); in computeOperandLatency()
222 if (SCDesc->isValid() && !DefMI->getOperand(DefOperIdx).isImplicit() && in computeOperandLatency()
223 !DefMI->getDesc().operands()[DefOperIdx].isOptionalDef() && in computeOperandLatency()
226 << *DefMI << " (Try with MCSchedModel.CompleteModel set to false)"; in computeOperandLatency()
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H A DLiveRangeEdit.cpp72 const MachineInstr *DefMI) { in checkRematerializable() argument
73 assert(DefMI && "Missing instruction"); in checkRematerializable()
75 if (!TII.isTriviallyReMaterializable(*DefMI)) in checkRematerializable()
90 MachineInstr *DefMI = LIS.getInstructionFromIndex(OrigVNI->def); in scanRemattable() local
91 if (!DefMI) in scanRemattable()
93 checkRematerializable(OrigVNI, DefMI); in scanRemattable()
205 MachineInstr *DefMI = nullptr, *UseMI = nullptr; in foldAsLoad() local
211 if (DefMI && DefMI != MI) in foldAsLoad()
215 DefMI = MI; in foldAsLoad()
225 if (!DefMI || !UseMI) in foldAsLoad()
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H A DMachineLateInstrsCleanup.cpp152 MachineInstr *DefMI = MBBDefs[Reg]; in clearKillsForDef() local
153 assert(DefMI->isIdenticalTo(*ToRemoveMI) && "Previous def not identical?"); in clearKillsForDef()
154 if (DefMI->getParent() == MBB) in clearKillsForDef()
211 for (auto [Reg, DefMI] : RegDefs[FirstPred->getNumber()]) in processBlock()
214 [&, &Reg = Reg, &DefMI = DefMI](const MachineBasicBlock *Pred) { in processBlock()
215 return RegDefs[Pred->getNumber()].hasIdentical(Reg, DefMI); in processBlock()
217 MBBDefs[Reg] = DefMI; in processBlock()
219 << printMBBReference(*MBB) << ": " << *DefMI); in processBlock()
H A DMachineTraceMetrics.cpp675 const MachineInstr *DefMI; member
679 DataDep(const MachineInstr *DefMI, unsigned DefOp, unsigned UseOp) in DataDep()
680 : DefMI(DefMI), DefOp(DefOp), UseOp(UseOp) {} in DataDep()
688 DefMI = DefMO->getParent(); in DataDep()
811 const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg); in computeCrossBlockCriticalPath() local
813 const TraceBlockInfo &DefTBI = BlockInfo[DefMI->getParent()->getNumber()]; in computeCrossBlockCriticalPath()
816 unsigned Len = LIR.Height + Cycles[DefMI].Depth; in computeCrossBlockCriticalPath()
836 BlockInfo[Dep.DefMI->getParent()->getNumber()]; in updateDepth()
841 unsigned DepCycle = Cycles.lookup(Dep.DefMI).Depth; in updateDepth()
843 if (!Dep.DefMI->isTransient()) in updateDepth()
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H A DRegisterCoalescer.cpp858 MachineInstr *DefMI = LIS->getInstructionFromIndex(AValNo->def); in removeCopyByCommutingDef() local
859 if (!DefMI) in removeCopyByCommutingDef()
861 if (!DefMI->isCommutable()) in removeCopyByCommutingDef()
865 int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg(), /*TRI=*/nullptr); in removeCopyByCommutingDef()
868 if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) in removeCopyByCommutingDef()
881 if (!TII->findCommutedOpIndices(*DefMI, UseOpIdx, NewDstIdx)) in removeCopyByCommutingDef()
884 MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); in removeCopyByCommutingDef()
909 << *DefMI); in removeCopyByCommutingDef()
913 MachineBasicBlock *MBB = DefMI->getParent(); in removeCopyByCommutingDef()
915 TII->commuteInstruction(*DefMI, false, UseOpIdx, NewDstIdx); in removeCopyByCommutingDef()
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H A DPHIElimination.cpp230 MachineInstr *DefMI = MRI->getVRegDef(VirtReg); in run() local
231 if (!DefMI) in run()
242 MachineBasicBlock *DefMBB = DefMI->getParent(); in run()
267 for (MachineInstr *DefMI : ImpDefs) { in run()
268 Register DefReg = DefMI->getOperand(0).getReg(); in run()
271 LIS->RemoveMachineInstrFromMaps(*DefMI); in run()
272 DefMI->eraseFromParent(); in run()
601 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerPHINode() local
602 if (DefMI->isImplicitDef()) in LowerPHINode()
603 ImpDefs.insert(DefMI); in LowerPHINode()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp65 bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
145 MachineInstr &DefMI) { in tryToTuneBranch() argument
147 if (MI.getParent() != DefMI.getParent()) in tryToTuneBranch()
153 switch (DefMI.getOpcode()) { in tryToTuneBranch()
199 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
202 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
206 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting, /*Is64Bit=*/false); in tryToTuneBranch()
254 if (isNZCVTouchedInInstructionRange(DefMI, MI, TRI)) in tryToTuneBranch()
257 LLVM_DEBUG(DefMI.print(dbgs())); in tryToTuneBranch()
261 NewCmp = convertToFlagSetting(DefMI, IsFlagSetting, /*Is64Bit=*/true); in tryToTuneBranch()
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H A DAArch64Subtarget.cpp559 const MachineInstr *DefMI = Def->getInstr(); in adjustSchedDependency() local
560 if (DefMI->getOpcode() == TargetOpcode::BUNDLE) { in adjustSchedDependency()
561 Register Reg = DefMI->getOperand(DefOpIdx).getReg(); in adjustSchedDependency()
562 for (const auto &Op : const_mi_bundle_ops(*DefMI)) { in adjustSchedDependency()
564 DefMI = Op.getParent(); in adjustSchedDependency()
584 SchedModel->computeOperandLatency(DefMI, DefOpIdx, UseMI, UseOpIdx)); in adjustSchedDependency()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86OptimizeLEAs.cpp350 for (auto *DefMI : List) { in chooseBestLEA() local
352 int64_t AddrDispShiftTemp = getAddrDispShift(MI, MemOpNo, *DefMI, 1); in chooseBestLEA()
364 MRI->getRegClass(DefMI->getOperand(0).getReg())) in chooseBestLEA()
371 int DistTemp = calcInstrDist(*DefMI, MI); in chooseBestLEA()
381 BestLEA = DefMI; in chooseBestLEA()
525 MachineInstr *DefMI; in removeRedundantAddrCalc() local
528 if (!chooseBestLEA(Insns->second, MI, DefMI, AddrDispShift, Dist)) in removeRedundantAddrCalc()
538 DefMI->removeFromParent(); in removeRedundantAddrCalc()
539 MBB->insert(MachineBasicBlock::iterator(&MI), DefMI); in removeRedundantAddrCalc()
540 InstrPos[DefMI] = InstrPos[&MI] - 1; in removeRedundantAddrCalc()
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H A DX86TileConfig.cpp216 for (auto &DefMI : MRI.def_instructions(R)) { in runOnMachineFunction() local
217 MachineBasicBlock &MBB = *DefMI.getParent(); in runOnMachineFunction()
218 if (DefMI.isMoveImmediate()) { in runOnMachineFunction()
221 assert(Imm == DefMI.getOperand(1).getImm() && in runOnMachineFunction()
225 if (DefMI.getOperand(1).isImm()) { in runOnMachineFunction()
226 Imm = DefMI.getOperand(1).getImm(); in runOnMachineFunction()
228 assert(DefMI.getOpcode() == X86::MOV32r0 && in runOnMachineFunction()
246 auto Iter = DefMI.getIterator(); in runOnMachineFunction()
H A DX86PreTileConfig.cpp249 MachineInstr *DefMI = MRI->getVRegDef(R); in INITIALIZE_PASS_DEPENDENCY() local
250 assert(DefMI && "R must has one define instruction"); in INITIALIZE_PASS_DEPENDENCY()
251 MachineBasicBlock *DefMBB = DefMI->getParent(); in INITIALIZE_PASS_DEPENDENCY()
252 if (DefMI->isMoveImmediate() || !DefVisited.insert(DefMI).second) in INITIALIZE_PASS_DEPENDENCY()
256 if (DefMI->getOpcode() == X86::COPY) { in INITIALIZE_PASS_DEPENDENCY()
257 MachineInstr *MI = MRI->getVRegDef(DefMI->getOperand(1).getReg()); in INITIALIZE_PASS_DEPENDENCY()
262 if (DefMI->isPHI()) { in INITIALIZE_PASS_DEPENDENCY()
263 for (unsigned I = 1; I < DefMI->getNumOperands(); I += 2) in INITIALIZE_PASS_DEPENDENCY()
264 if (isLoopBackEdge(DefMBB, DefMI->getOperand(I + 1).getMBB())) in INITIALIZE_PASS_DEPENDENCY()
265 RecordShape(DefMI, DefMBB); // In this case, PHI is also a shape def. in INITIALIZE_PASS_DEPENDENCY()
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H A DX86CallFrameOptimization.cpp609 MachineInstr &DefMI = *MRI->getVRegDef(Reg); in canFoldIntoRegPush() local
613 if ((DefMI.getOpcode() != X86::MOV32rm && in canFoldIntoRegPush()
614 DefMI.getOpcode() != X86::MOV64rm) || in canFoldIntoRegPush()
615 DefMI.getParent() != FrameSetup->getParent()) in canFoldIntoRegPush()
620 for (MachineBasicBlock::iterator I = DefMI; I != FrameSetup; ++I) in canFoldIntoRegPush()
624 return &DefMI; in canFoldIntoRegPush()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp280 MachineInstr *DefMI = MRI.getVRegDef(Reg); in isCallViaRegister() local
282 assert(DefMI); in isCallViaRegister()
286 if (!DefMI->mayLoad() || DefMI->getNumOperands() < 3) in isCallViaRegister()
289 unsigned Flags = DefMI->getOperand(2).getTargetFlags(); in isCallViaRegister()
295 assert(DefMI->hasOneMemOperand()); in isCallViaRegister()
296 Val = (*DefMI->memoperands_begin())->getValue(); in isCallViaRegister()
298 Val = (*DefMI->memoperands_begin())->getPseudoValue(); in isCallViaRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURewriteAGPRCopyMFMA.cpp123 MachineInstr *DefMI = LIS.getInstructionFromIndex(VNI->def); in run() local
127 if (!DefMI || !DefMI->isFullCopy()) in run()
130 Register CopySrcReg = DefMI->getOperand(1).getReg(); in run()
216 LIS.RemoveMachineInstrFromMaps(*DefMI); in run()
217 DefMI->eraseFromParent(); in run()
H A DSIFixSGPRCopies.cpp740 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg()); in run() local
741 if (DefMI && TII->isFoldableCopy(*DefMI)) { in run()
742 const MachineOperand &Def = DefMI->getOperand(0); in run()
746 const MachineOperand &Copied = DefMI->getOperand(1); in run()
840 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(I).getReg()); in processPHINode() local
841 if (DefMI && DefMI->isPHI()) in processPHINode()
842 PHIOperands.insert(DefMI); in processPHINode()
863 MachineInstr *DefMI = MRI->getVRegDef(MaybeVGPRConstMO.getReg()); in tryMoveVGPRConstToSGPR() local
864 if (!DefMI || !DefMI->isMoveImmediate()) in tryMoveVGPRConstToSGPR()
867 MachineOperand *SrcConst = TII->getNamedOperand(*DefMI, AMDGPU::OpName::src0); in tryMoveVGPRConstToSGPR()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp646 MachineInstr *DefMI = MRI->getVRegDef(TrueReg1); in simplifyCode() local
648 if (!DefMI) in simplifyCode()
651 unsigned DefOpc = DefMI->getOpcode(); in simplifyCode()
661 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); in simplifyCode()
685 Register DefReg1 = DefMI->getOperand(1).getReg(); in simplifyCode()
686 Register DefReg2 = DefMI->getOperand(2).getReg(); in simplifyCode()
687 unsigned DefImmed = DefMI->getOperand(3).getImm(); in simplifyCode()
736 .add(DefMI->getOperand(1)); in simplifyCode()
737 addRegToUpdate(DefMI->getOperand(0).getReg()); in simplifyCode()
738 addRegToUpdate(DefMI->getOperand(1).getReg()); in simplifyCode()
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H A DPPCVSXSwapRemoval.cpp618 MachineInstr* DefMI = MRI->getVRegDef(Reg); in formWebs() local
619 assert(SwapMap.contains(DefMI) && in formWebs()
621 int DefIdx = SwapMap[DefMI]; in formWebs()
629 LLVM_DEBUG(DefMI->dump()); in formWebs()
723 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in recordUnoptimizableWebs() local
724 Register DefReg = DefMI->getOperand(0).getReg(); in recordUnoptimizableWebs()
725 int DefIdx = SwapMap[DefMI]; in recordUnoptimizableWebs()
735 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
754 LLVM_DEBUG(DefMI->dump()); in recordUnoptimizableWebs()
800 MachineInstr *DefMI = MRI->getVRegDef(UseReg); in markSwapsForRemoval() local
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H A DPPCInstrInfo.h299 bool simplifyToLI(MachineInstr &MI, MachineInstr &DefMI,
303 bool transformToNewImmFormFedByAdd(MachineInstr &MI, MachineInstr &DefMI,
309 MachineInstr &DefMI) const;
313 unsigned ConstantOpNo, MachineInstr &DefMI,
328 bool isDefMIElgibleForForwarding(MachineInstr &DefMI,
333 const MachineInstr &DefMI,
338 const MachineInstr &DefMI,
448 const MachineInstr &DefMI,
461 const MachineInstr &DefMI, in hasLowDefLatency() argument
607 bool foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, Register Reg,
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H A DPPCInstrInfo.cpp167 const InstrItineraryData *ItinData, const MachineInstr &DefMI, in getOperandLatency() argument
170 ItinData, DefMI, DefIdx, UseMI, UseIdx); in getOperandLatency()
172 if (!DefMI.getParent()) in getOperandLatency()
175 const MachineOperand &DefMO = DefMI.getOperand(DefIdx); in getOperandLatency()
181 &DefMI.getParent()->getParent()->getRegInfo(); in getOperandLatency()
191 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
730 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getConstantFromConstantPool() local
731 for (auto MO2 : DefMI->uses()) in getConstantFromConstantPool()
2070 bool PPCInstrInfo::onlyFoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, in onlyFoldImmediate() argument
2073 unsigned DefOpc = DefMI.getOpcode(); in onlyFoldImmediate()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp498 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI); in optimizeSelect() local
499 bool Invert = !DefMI; in optimizeSelect()
500 if (!DefMI) in optimizeSelect()
501 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI); in optimizeSelect()
502 if (!DefMI) in optimizeSelect()
514 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg); in optimizeSelect()
517 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
520 NewMI.add(DefMI->getOperand(i)); in optimizeSelect()
538 SeenMIs.erase(DefMI); in optimizeSelect()
544 if (DefMI->getParent() != MI.getParent()) in optimizeSelect()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVRegisterBankInfo.cpp368 MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(0).getReg()); in getInstrMapping() local
369 if (onlyDefinesFP(*DefMI, MRI, TRI)) in getInstrMapping()
423 MachineInstr *DefMI = MRI.getVRegDef(VReg); in getInstrMapping() local
425 onlyDefinesFP(*DefMI, MRI, TRI)) in getInstrMapping()
494 MachineInstr *DefMI = MRI.getVRegDef(MI.getOperand(1).getReg()); in getInstrMapping() local
496 onlyDefinesFP(*DefMI, MRI, TRI)) { in getInstrMapping()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DUtils.cpp469 auto *DefMI = MRI.getVRegDef(Reg); in getDefSrcRegIgnoringCopies() local
470 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg()); in getDefSrcRegIgnoringCopies()
473 unsigned Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
475 Register SrcReg = DefMI->getOperand(1).getReg(); in getDefSrcRegIgnoringCopies()
479 DefMI = MRI.getVRegDef(SrcReg); in getDefSrcRegIgnoringCopies()
481 Opc = DefMI->getOpcode(); in getDefSrcRegIgnoringCopies()
483 return DefinitionAndSourceRegister{DefMI, DefSrcReg}; in getDefSrcRegIgnoringCopies()
647 MachineInstr *DefMI = getDefIgnoringCopies(Reg, MRI); in getOpcodeDef() local
648 return DefMI && DefMI->getOpcode() == Opcode ? DefMI : nullptr; in getOpcodeDef()
811 const MachineInstr *DefMI = MRI.getVRegDef(Val); in isKnownNeverNaN() local
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