Searched refs:DefInstr (Results 1 – 9 of 9) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | MachineCombiner.cpp | 151 MachineInstr *DefInstr = nullptr; in getOperandDef() local
154 DefInstr = MRI->getUniqueVRegDef(MO.getReg()); in getOperandDef()
155 return DefInstr; in getOperandDef()
225 MachineInstr *DefInstr = InsInstrs[II->second]; in getDepth() local
226 assert(DefInstr && in getDepth()
230 DefInstr->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr); in getDepth()
233 LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx, in getDepth()
236 MachineInstr *DefInstr = getOperandDef(MO); in getDepth() local
237 if (DefInstr && (TII->getMachineCombinerTraceStrategy() != in getDepth()
239 DefInstr->getParent() == &MBB)) { in getDepth()
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| H A D | LiveRangeShrink.cpp | 218 MachineInstr &DefInstr = *MRI.def_instr_begin(Reg); in runOnMachineFunction() local
219 if (!TII.isCopyInstr(DefInstr)) in runOnMachineFunction()
221 Insert = FindDominatedInstruction(DefInstr, Insert, IOM); in runOnMachineFunction()
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| H A D | MachineUniformityAnalysis.cpp | 146 auto *DefInstr = Def->getParent(); in isDivergentUse() local
148 return isTemporalDivergent(*UseInstr->getParent(), *DefInstr); in isDivergentUse()
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| H A D | ScheduleDAGInstrs.cpp | 338 MachineInstr *DefInstr = DefSU->getInstr(); in addPhysRegDeps() local
339 MachineOperand &DefMO = DefInstr->getOperand(I->OpIdx); in addPhysRegDeps()
345 SchedModel.computeOutputLatency(MI, OperIdx, DefInstr)); in addPhysRegDeps()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | UniformityAnalysis.cpp | 97 if (const auto *DefInstr = dyn_cast<Instruction>(V)) { in isDivergentUse() local
99 return isTemporalDivergent(*UseInstr->getParent(), *DefInstr); in isDivergentUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIWholeQuadMode.cpp | 1622 MachineInstr *DefInstr = MRI->getVRegDef(InputReg); in lowerInitExec() local
1623 assert(DefInstr && DefInstr->isCopy()); in lowerInitExec()
1624 if (DefInstr->getParent() == MBB) { in lowerInitExec()
1625 if (DefInstr != FirstMI) { in lowerInitExec()
1628 DefInstr->removeFromParent(); in lowerInitExec()
1629 MBB->insert(FirstMI, DefInstr); in lowerInitExec()
1631 LIS->handleMove(*DefInstr); in lowerInitExec()
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| H A D | SIPeepholeSDWA.cpp | 316 MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg->getReg()); in findSingleRegDef() local
317 if (!DefInstr) in findSingleRegDef()
320 for (auto &DefMO : DefInstr->defs()) { in findSingleRegDef()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVPreLegalizer.cpp | 323 if (MachineInstr *DefInstr = in propagateSPIRVType() local
325 if (SPIRVType *Def = propagateSPIRVType(DefInstr, GR, MRI, MIB)) { in propagateSPIRVType()
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| H A D | SPIRVBuiltins.cpp | 2375 MachineInstr *DefInstr = MRI->getUniqueVRegDef(GlobalWorkSize); in buildNDRange() local
2376 assert(DefInstr && isSpvIntrinsic(*DefInstr, Intrinsic::spv_gep) && in buildNDRange()
2377 DefInstr->getOperand(3).isReg()); in buildNDRange()
2378 Register GWSPtr = DefInstr->getOperand(3).getReg(); in buildNDRange()
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