154   MachineInstr *DefInstr = nullptr;  in getOperandDef()  local
157     DefInstr = MRI->getUniqueVRegDef(MO.getReg());  in getOperandDef()
158   return DefInstr;  in getOperandDef()
228         MachineInstr *DefInstr = InsInstrs[II->second];  in getDepth()  local
229         assert(DefInstr &&  in getDepth()
233             DefInstr->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr);  in getDepth()
236         LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx,  in getDepth()
239         MachineInstr *DefInstr = getOperandDef(MO);  in getDepth()  local
240         if (DefInstr && (TII->getMachineCombinerTraceStrategy() !=  in getDepth()
242                          DefInstr->getParent() == &MBB)) {  in getDepth()
243           DepthOp = BlockTrace.getInstrCycles(*DefInstr).Depth;  in getDepth()
244           if (!isTransientMI(DefInstr))  in getDepth()
246                 DefInstr,  in getDepth()
247                 DefInstr->findRegisterDefOperandIdx(MO.getReg(),  in getDepth()