| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFMISimplifyPatchable.cpp | 145 MachineInstr *DefInst = MO.getParent(); in checkADDrr() local 146 unsigned Opcode = DefInst->getOpcode(); in checkADDrr() 158 const MachineOperand &ImmOp = DefInst->getOperand(2); in checkADDrr() 166 const MachineOperand &Opnd = DefInst->getOperand(0); in checkADDrr() 171 BuildMI(*DefInst->getParent(), *DefInst, DefInst->getDebugLoc(), TII->get(COREOp)) in checkADDrr() 172 .add(DefInst->getOperand(0)).addImm(Opcode).add(*BaseOp) in checkADDrr() 174 DefInst->eraseFromParent(); in checkADDrr() 335 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg); in removeLD() local 336 if (!DefInst) in removeLD() 339 if (DefInst->getOpcode() != BPF::LD_imm64) in removeLD() [all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | DeadStoreElimination.cpp | 877 DefInst = MemDef->getMemoryInst(); in MemoryLocationWrapper() 883 Instruction *DefInst; member 892 DefInst = MemDef->getMemoryInst(); in MemoryDefWrapper() 897 Instruction *DefInst; member 1299 bool isCompleteOverwrite(const MemoryLocation &DefLoc, Instruction *DefInst, in isCompleteOverwrite() 1313 return isOverwrite(UseInst, DefInst, *CC, DefLoc, InstWriteOffset, in isCompleteOverwrite() 2272 Instruction *DefInst = Def->getMemoryInst(); in eliminateRedundantStoresOfExistingValues() local 2273 auto MaybeDefLoc = getLocForWrite(DefInst); in eliminateRedundantStoresOfExistingValues() 2274 if (!MaybeDefLoc || !isRemovable(DefInst)) in eliminateRedundantStoresOfExistingValues() 2291 if (DefInst->isIdenticalToWhenDefined(UpperInst, in eliminateRedundantStoresOfExistingValues() [all …]
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| H A D | EarlyCSE.cpp | 674 Instruction *DefInst = nullptr; member 683 : DefInst(Inst), Generation(Generation), MatchingId(MatchingId), in LoadValue() 1240 if (InVal.DefInst == nullptr) in getMatchingValue() 1255 Instruction *Matching = MemInstMatching ? MemInst.get() : InVal.DefInst; in getMatchingValue() 1256 Instruction *Other = MemInstMatching ? InVal.DefInst : MemInst.get(); in getMatchingValue() 1264 if (MemInst.isStore() && InVal.DefInst != Result) in getMatchingValue() 1273 if (!isNonTargetIntrinsicMatch(cast<IntrinsicInst>(InVal.DefInst), in getMatchingValue() 1279 !isSameMemGeneration(InVal.Generation, CurrentGeneration, InVal.DefInst, in getMatchingValue() 1595 << " to: " << *InVal.DefInst << '\n'); in processNode() 1715 if (InVal.DefInst && in processNode() [all …]
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| H A D | NewGVN.cpp | 4002 auto *DefInst = dyn_cast_or_null<Instruction>(Def); in eliminateInstructions() local 4003 if (DefInst && AllTempInstructions.count(DefInst)) { in eliminateInstructions() 4004 auto *PN = cast<PHINode>(DefInst); in eliminateInstructions()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUMemoryUtils.cpp | 344 Instruction *DefInst = Def->getMemoryInst(); in isReallyAClobber() local 346 if (isa<FenceInst>(DefInst)) in isReallyAClobber() 349 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(DefInst)) { in isReallyAClobber() 373 if (checkNoAlias(dyn_cast<AtomicCmpXchgInst>(DefInst)) || in isReallyAClobber() 374 checkNoAlias(dyn_cast<AtomicRMWInst>(DefInst))) in isReallyAClobber()
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| H A D | SIPeepholeSDWA.cpp | 675 const MachineInstr *DefInst = Def.getParent(); in foldToImm() local 676 if (!TII->isFoldableCopy(*DefInst)) in foldToImm() 679 const MachineOperand &Copied = DefInst->getOperand(1); in foldToImm()
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| H A D | SIInstrInfo.cpp | 9809 auto *DefInst = MRI.getVRegDef(RSR.Reg); in getVRegSubRegDef() local 9810 while (auto *MI = DefInst) { in getVRegSubRegDef() 9811 DefInst = nullptr; in getVRegSubRegDef() 9820 DefInst = MRI.getVRegDef(RSR.Reg); in getVRegSubRegDef() 9828 DefInst = MRI.getVRegDef(RSR.Reg); in getVRegSubRegDef() 9831 if (!DefInst) in getVRegSubRegDef()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCPreEmitPeephole.cpp | 253 MachineBasicBlock::iterator DefInst; in addLinkerOpt() member 315 MachineBasicBlock::iterator BBI = Pair->DefInst; in addLinkerOpt() 338 Pair->DefInst->addOperand(ImplDef); in addLinkerOpt() 346 Pair->DefInst->addOperand(*MF, PCRelLabel); in addLinkerOpt()
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| H A D | PPCBranchCoalescing.cpp | 462 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg()); in canMoveToEnd() local 463 if (DefInst->isPHI() && DefInst->getParent() == MI.getParent()) { in canMoveToEnd()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonCopyToCombine.cpp | 400 MachineInstr *DefInst = LastDef[Reg]; in findPotentialNewifiableTFRs() local 401 if (!DefInst) in findPotentialNewifiableTFRs() 403 if (!isCombinableInstType(*DefInst, TII, ShouldCombineAggressively)) in findPotentialNewifiableTFRs() 408 MachineBasicBlock::iterator It(DefInst); in findPotentialNewifiableTFRs() 419 PotentiallyNewifiableTFR.insert(DefInst); in findPotentialNewifiableTFRs()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 521 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveOut() local 522 if (DefInst.getParent() != MBB) { in mayLiveOut() 526 if (!SelfLoopDef || dominates(PosIndexes, DefInst, *SelfLoopDef)) in mayLiveOut() 527 SelfLoopDef = &DefInst; in mayLiveOut() 569 for (const MachineInstr &DefInst : MRI->def_instructions(VirtReg)) { in mayLiveIn() local 570 if (DefInst.getParent() != MBB || ++C >= Limit) { in mayLiveIn()
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| H A D | ModuloSchedule.cpp | 2344 MachineInstr *DefInst = MRI.getVRegDef(OrigReg); in updateInstrUse() local 2345 if (!DefInst || DefInst->getParent() != OrigKernel) in updateInstrUse() 2349 if (DefInst->isPHI()) { in updateInstrUse() 2352 getPhiRegs(*DefInst, OrigKernel, InitReg, LoopReg); in updateInstrUse() 2355 DefInst = MRI.getVRegDef(LoopReg); in updateInstrUse() 2357 unsigned DefStageNum = Schedule.getStage(DefInst); in updateInstrUse()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | MemorySSA.cpp | 284 Instruction *DefInst = MD->getMemoryInst(); in instructionClobbersQuery() local 285 assert(DefInst && "Defining instruction not actually an instruction"); in instructionClobbersQuery() 287 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(DefInst)) { in instructionClobbersQuery() 314 ModRefInfo I = AA.getModRefInfo(DefInst, CB); in instructionClobbersQuery() 318 if (auto *DefLoad = dyn_cast<LoadInst>(DefInst)) in instructionClobbersQuery() 322 ModRefInfo I = AA.getModRefInfo(DefInst, UseLoc); in instructionClobbersQuery()
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