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Searched refs:DRC (Results 1 – 15 of 15) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCondMov.td18 class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
20 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
26 class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
28 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
61 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
62 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
63 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
[all …]
H A DMipsInstrFPU.td216 class LWXC1_FT<string opstr, RegisterOperand DRC,
218 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
220 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
225 class SWXC1_FT<string opstr, RegisterOperand DRC,
227 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
H A DMipsInstrInfo.td1809 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1810 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1811 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> {
1828 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1829 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1830 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> {
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp153c-dhcor-drc-compact.dts8 * DRC Compact PCB number: 627-100 or newer
19 model = "DH electronics STM32MP153C DHCOR DRC Compact";
/freebsd/sys/dev/sound/macio/
H A Dtumbler.c181 u_char DRC[2]; member
227 sizeof tumbler_initdata.DRC, /* 0x02 */
357 tumbler_write(sc, TUMBLER_DRC, tumbler_initdata.DRC); in tumbler_init()
H A Dsnapper.c191 u_char DRC[6]; member
253 sizeof snapper_initdata.DRC, /* 0x02 */
405 snapper_write(sc, SNAPPER_DRC, snapper_initdata.DRC); in snapper_init()
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dexynos4-fimc-is.txt5 processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp203 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
776 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux() argument
779 switch (DRC->getID()) { in buildMux()
800 Register MuxR = MRI->createVirtualRegister(DRC); in buildMux()
H A DHexagonBitSimplify.cpp961 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
962 if (!DRC) in isTransparentCopy()
965 return DRC == getFinalVRegClass(RS, MRI); in isTransparentCopy()
1511 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
1512 if (HBS::getConst(DRC, 0, DRC.width(), U)) { in processBlock()
1519 BT.put(ImmReg, DRC); in processBlock()
/freebsd/contrib/file/magic/Magdir/
H A Dringdove41 >0 regex begin\ drc\ v with PCB DRC script
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td1011 class AtomicLoad<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1012 : Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
1013 [(set DRC:$rd, (Op i16:$rr))]>;
1015 class AtomicStore<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1016 : Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
1017 [(Op DRC:$rr, i16:$rd)]>;
1019 class AtomicLoadOp<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
1020 : Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand), "atomic_op",
1021 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineVerifier.cpp2510 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2512 if (!DRC->contains(Reg)) { in visitMachineOperand()
2515 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2625 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2634 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
2635 if (!DRC) { in visitMachineOperand()
2640 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
2642 errs() << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
H A DMachineSink.cpp345 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in PerformTrivialForwardCoalescing() local
346 if (SRC != DRC) in PerformTrivialForwardCoalescing()
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dexynos5433-clock.txt47 which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp5699 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
5701 return DRC->contains(Reg); in isLegalRegOperand()
5711 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
5712 if (!DRC) in isLegalRegOperand()
5715 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()