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Searched refs:DRC (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCondMov.td18 class CMov_I_I_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
20 InstSE<(outs DRC:$rd), (ins DRC:$rs, CRC:$rt, DRC:$F),
26 class CMov_I_F_FT<string opstr, RegisterOperand CRC, RegisterOperand DRC,
28 InstSE<(outs DRC:$fd), (ins DRC:$fs, CRC:$rt, DRC:$F),
55 multiclass MovzPats0<RegisterClass CRC, RegisterClass DRC,
59 def : MipsPat<(select (i32 (setge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
60 (MOVZInst DRC:$T, (SLTOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
61 def : MipsPat<(select (i32 (setuge CRC:$lhs, CRC:$rhs)), DRC:$T, DRC:$F),
62 (MOVZInst DRC:$T, (SLTuOp CRC:$lhs, CRC:$rhs), DRC:$F)>;
63 def : MipsPat<(select (i32 (setge CRC:$lhs, immSExt16:$rhs)), DRC:$T, DRC:$F),
[all …]
H A DMipsInstrFPU.td216 class LWXC1_FT<string opstr, RegisterOperand DRC,
218 InstSE<(outs DRC:$fd), (ins PtrRC:$base, PtrRC:$index),
220 [(set DRC:$fd, (OpNode (add iPTR:$base, iPTR:$index)))], Itin,
225 class SWXC1_FT<string opstr, RegisterOperand DRC,
227 InstSE<(outs), (ins DRC:$fs, PtrRC:$base, PtrRC:$index),
229 [(OpNode DRC:$fs, (add iPTR:$base, iPTR:$index))], Itin,
H A DMipsInstrInfo.td1821 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1822 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1823 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]> {
1840 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1841 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1842 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]> {
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstm32mp153c-dhcor-drc-compact.dts8 * DRC Compact PCB number: 627-100 or newer
19 model = "DH electronics STM32MP153C DHCOR DRC Compact";
/freebsd/sys/dev/sound/macio/
H A Dtumbler.c176 #define TUMBLER_DRC_ENABLE 0x01 /* enable DRC */
185 uint8_t DRC[2]; member
208 { TUMBLER_DRC_COMP_31, TUMBLER_DRC_DEFL_TH }, /* DRC */
231 sizeof tumbler_initdata.DRC, /* 0x02 */
382 tumbler_write(sc, TUMBLER_DRC, tumbler_initdata.DRC); in tumbler_init()
H A Dsnapper.c195 uint8_t DRC[6]; member
226 { 1, 0, 0, 0, 0, 0 }, /* DRC */
257 sizeof snapper_initdata.DRC, /* 0x02 */
430 snapper_write(sc, SNAPPER_DRC, snapper_initdata.DRC); in snapper_init()
/freebsd/sys/contrib/device-tree/Bindings/media/
H A Dexynos4-fimc-is.txt5 processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonEarlyIfConv.cpp196 const TargetRegisterClass *DRC, unsigned PredR, unsigned TR,
769 MachineBasicBlock::iterator At, const TargetRegisterClass *DRC, in buildMux() argument
772 switch (DRC->getID()) { in buildMux()
793 Register MuxR = MRI->createVirtualRegister(DRC); in buildMux()
H A DHexagonBitSimplify.cpp939 auto *DRC = getFinalVRegClass(RD, MRI); in isTransparentCopy() local
940 if (!DRC) in isTransparentCopy()
943 return DRC == getFinalVRegClass(RS, MRI); in isTransparentCopy()
1489 const BitTracker::RegisterCell &DRC = BT.lookup(DR); in processBlock() local
1490 if (HBS::getConst(DRC, 0, DRC.width(), U)) { in processBlock()
1497 BT.put(ImmReg, DRC); in processBlock()
/freebsd/contrib/file/magic/Magdir/
H A Dringdove41 >0 regex begin\ drc\ v with PCB DRC script
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRInstrInfo.td990 class AtomicLoad<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
991 : Pseudo<(outs DRC:$rd), (ins PTRRC:$rr), "atomic_op",
992 [(set DRC:$rd, (Op i16:$rr))]>;
994 class AtomicStore<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
995 : Pseudo<(outs), (ins PTRRC:$rd, DRC:$rr), "atomic_op",
996 [(Op DRC:$rr, i16:$rd)]>;
998 class AtomicLoadOp<PatFrag Op, RegisterClass DRC, RegisterClass PTRRC>
999 : Pseudo<(outs DRC:$rd), (ins PTRRC:$rr, DRC:$operand), "atomic_op",
1000 [(set DRC:$rd, (Op i16:$rr, DRC:$operand))]>;
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineVerifier.cpp2638 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2640 if (!DRC->contains(Reg)) { in visitMachineOperand()
2643 << TRI->getRegClassName(DRC) << " register.\n"; in visitMachineOperand()
2754 if (const TargetRegisterClass *DRC = in visitMachineOperand() local
2763 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
2764 if (!DRC) { in visitMachineOperand()
2769 if (!RC->hasSuperClassEq(DRC)) { in visitMachineOperand()
2771 OS << "Expected a " << TRI->getRegClassName(DRC) in visitMachineOperand()
H A DMachineSink.cpp385 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in PerformTrivialForwardCoalescing() local
386 if (SRC != DRC) in PerformTrivialForwardCoalescing()
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dexynos5433-clock.txt47 which generates clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp5951 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass); in isLegalRegOperand() local
5953 return DRC->contains(Reg); in isLegalRegOperand()
5963 DRC = RI.getMatchingSuperRegClass(SuperRC, DRC, MO.getSubReg()); in isLegalRegOperand()
5964 if (!DRC) in isLegalRegOperand()
5967 return RC->hasSuperClassEq(DRC); in isLegalRegOperand()
/freebsd/contrib/llvm-project/clang/lib/Serialization/
H A DASTWriter.cpp8916 const auto *DRC = cast<OpenACCDeviceResidentClause>(C); in writeOpenACCClause() local
8917 writeSourceLocation(DRC->getLParenLoc()); in writeOpenACCClause()
8918 writeOpenACCVarList(DRC); in writeOpenACCClause()