| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ |
| H A D | synopsys.txt | 3 The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit
6 The Zynq DDR ECC controller has an optional ECC support in half-bus width
14 - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller
15 - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller
16 - reg: Should contain DDR controller registers location and length.
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| H A D | ath79-ddr-controller.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the AR7xxx and AR9xxx families provides an interface
4 to flush the FIFO between various devices and the DDR. This is mainly used
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| H A D | brcm,dpfe-cpu.txt | 1 DDR PHY Front End (DPFE) for Broadcom STB
5 communicate with the DCPU, which resides inside the DDR PHY.
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| /freebsd/sys/contrib/device-tree/Bindings/mips/brcm/ |
| H A D | soc.txt | 45 independently (control registers, DDR PHYs, etc.). One might consider
58 the entire memory controller (including all sub nodes: DDR PHY,
86 == DDR PHY control
88 Control registers for this memory controller's DDR PHY.
95 - reg : the DDR PHY register range and length
104 == DDR memory controller sequencer
106 Control registers for this memory controller's DDR memory sequencer
115 - reg : the DDR sequencer register range and length
136 - reg : the DDR Arbiter register range and length
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/fsl/ |
| H A D | ddr.txt | 1 Freescale DDR memory controller
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
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| H A D | mmdc.txt | 1 Freescale Multi Mode DDR controller (MMDC)
19 - reg : address and size of MMDC DDR controller registers
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | mvebu-core-clock.txt | 12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
37 2 = ddrclk (DDR clock)
44 3 = ddrclk (DDR controller clock derived from CPU0 clock)
49 2 = ddrclk (DDR controller clock derived from CPU0 clock)
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| H A D | brcm,bcm2835-cprman.txt | 27 - DSI0 DDR clock
30 - DSI1 DDR clock
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| H A D | armada3700-periph-clock.txt | 26 11 ddr_phy DDR PHY
27 12 ddr_fclk DDR F clock
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| H A D | qca,ath79-pll.txt | 3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
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| /freebsd/sys/contrib/device-tree/Bindings/arm/bcm/ |
| H A D | brcm,brcmstb.txt | 148 independently (control registers, DDR PHYs, etc.). One might consider
163 == DDR PHY control
165 Control registers for this memory controller's DDR PHY.
175 - reg : the DDR PHY register range
177 == DDR SHIMPHY
179 Control registers for this memory controller's DDR SHIMPHY.
183 - reg : the DDR SHIMPHY register range
185 == MEMC DDR control
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| /freebsd/sys/contrib/device-tree/Bindings/devfreq/ |
| H A D | rk3399_dmc.txt | 5 - devfreq-events: Node to get DDR loading, Refer to
21 It should be a DCF interrupt. When DDR DVFS finishes
26 Following properties relate to DDR timing:
65 When DDR frequency is less than DRAM_DLL_DISB_FREQ,
70 MHz (Mega Hz). When DDR frequency is less than
76 when the DDR frequency is less then ddr3_odt_dis_freq,
102 When DDR frequency is less then ddr3_odt_dis_freq,
128 MHz (Mega Hz). When the DDR frequency is less then
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| /freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ddr/ |
| H A D | lpddr3-timings.txt | 7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
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| H A D | lpddr2-timings.txt | 5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
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| /freebsd/sys/contrib/device-tree/Bindings/ddr/ |
| H A D | lpddr3-timings.txt | 7 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
8 - reg : maximum DDR clock frequency for the speed-bin. Type is <u32>
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| H A D | lpddr2-timings.txt | 5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | fsl,imx7ulp-pinctrl.txt | 4 ports and IOMUXC DDR for DDR interface.
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | bd9571mwv.txt | 28 - rohm,ddr-backup-power : Value to use for DDR-Backup Power (default 0).
29 This is a bitmask that specifies which DDR power
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| /freebsd/sys/contrib/device-tree/Bindings/mips/img/ |
| H A D | xilfpga.txt | 20 - 128Mbyte DDR RAM at 0x0000_0000
74 DDR initialization is already handled by a HW IP block.
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| /freebsd/sys/contrib/device-tree/Bindings/perf/ |
| H A D | fsl-imx-ddr.txt | 1 * Freescale(NXP) IMX8 DDR performance monitor
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| /freebsd/sys/contrib/device-tree/src/arm64/intel/ |
| H A D | keembay-evm.dts | 29 /* 2GB of DDR memory. */
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| /freebsd/sys/contrib/device-tree/Bindings/reset/ |
| H A D | amlogic,meson-axg-audio-arb.txt | 4 disables the access of Audio FIFOs to DDR on AXG based SoC.
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| /freebsd/sys/contrib/device-tree/Bindings/mips/ |
| H A D | ralink.txt | 26 of DDR and 8 MiB of flash (SPI NOR) and additional 128MiB SPI NAND
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| /freebsd/sys/contrib/device-tree/src/arm/ti/omap/ |
| H A D | dra76x-mmc-iodelay.dtsi | 15 * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | qca,ath79-cpu-intc.txt | 3 On most SoC the IRQ controller need to flush the DDR FIFO before running
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