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Searched refs:DATA0 (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/ntp/util/
H A Dtg.c72 #define DATA0 200 /* WWV/H 0 pulse */ macro
130 {DATA, DATA0}, /* 1 */
137 {DEC, DATA0}, /* 8 */
143 {DEC, DATA0}, /* 14 */
153 {DEC, DATA0}, /* 24 */
163 {DEC, DATA0}, /* 34 not used */
173 {DEC, DATA0}, /* 44 */
174 {DATA, DATA0}, /* 45 */
175 {DATA, DATA0}, /* 46 */
176 {DATA, DATA0}, /* 47 */
[all …]
H A Dtg2.c246 #define DATA0 (200) /* WWV/H 0 pulse */ macro
338 {DATA, DATA0}, /* 1 */
345 {DEC, DATA0}, /* 8 */
351 {DEC, DATA0}, /* 14 */
361 {DEC, DATA0}, /* 24 */
371 {DEC, DATA0}, /* 34 not used */
381 {DEC, DATA0}, /* 44 */
382 {DATA, DATA0}, /* 45 */
383 {DATA, DATA0}, /* 46 */
384 {DATA, DATA0}, /* 47 */
[all …]
/freebsd/sys/dev/smc/
H A Dif_smc.c632 smc_write_2(sc, DATA0, 0); in smc_task_tx()
633 smc_write_2(sc, DATA0, len); in smc_task_tx()
642 smc_write_multi_2(sc, DATA0, (uint16_t *)data, m->m_len / 2); in smc_task_tx()
650 smc_write_2(sc, DATA0, (CTRL_ODD << 8) | data[last_len - 1]); in smc_task_tx()
652 smc_write_2(sc, DATA0, 0); in smc_task_tx()
724 status = smc_read_2(sc, DATA0); in smc_task_rx()
725 len = smc_read_2(sc, DATA0) & RX_LEN_MASK; in smc_task_rx()
757 smc_read_multi_2(sc, DATA0, (uint16_t *)data, len >> 1); in smc_task_rx()
760 *data = smc_read_1(sc, DATA0); in smc_task_rx()
H A Dif_smcreg.h188 #define DATA0 0x8 macro
/freebsd/sys/contrib/device-tree/Bindings/display/ti/
H A Dti,omap3-dss.txt86 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
H A Dti,omap5-dss.txt77 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
H A Dti,omap4-dss.txt96 - lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddsi.txt68 The above mapping describes that the logical data lane DATA0 is mapped to
69 the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
/freebsd/sys/contrib/device-tree/src/arm/st/
H A Dstih407-pinctrl.dtsi738 DATA0 = <&pio11 3 ALT1 IN SE_NICLK_IO 0 CLK_A>;
766 DATA0 = <&pio12 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
794 DATA0 = <&pio14 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
867 DATA0 = <&pio12 7 ALT3 OUT SE_NICLK_IO 0 CLK_A>;
907 DATA0 = <&pio11 3 ALT3 IN SE_NICLK_IO 0 CLK_A>;
/freebsd/sys/dev/cxgbe/common/
H A Dt4_hw.c7082 t4_write_reg(adap, EPIO_REG(DATA0), mask0); in t4_wol_pat_enable()
7089 t4_write_reg(adap, EPIO_REG(DATA0), crc); in t4_wol_pat_enable()