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Searched refs:DAG (Results 1 – 25 of 261) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h143 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
179 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
181 SelectionDAG &DAG) const override;
183 SelectionDAG &DAG) const override;
190 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
191 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
192 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
193 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
194 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
195 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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H A DHexagonISelLoweringHVX.cpp509 const SDLoc &dl, SelectionDAG &DAG) const { in getInt()
511 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32)); in getInt()
513 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); in getInt()
550 SelectionDAG &DAG) const { in opCastElem()
554 return DAG.getBitcast(CastTy, Vec); in opCastElem()
559 SelectionDAG &DAG) const { in opJoin()
560 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
566 SelectionDAG &DAG) const { in opSplit()
570 return DAG.SplitVector(Vec, dl, Tys.first, Tys.second); in opSplit()
728 SelectionDAG &DAG) const { in convertToByteIndex()
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H A DHexagonISelLowering.cpp237 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) in LowerINTRINSIC_WO_CHAIN()
249 SelectionDAG &DAG, const SDLoc &dl) { in CreateCopyOfByValArgument() argument
250 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
251 return DAG.getMemcpy( in CreateCopyOfByValArgument()
278 const SDLoc &dl, SelectionDAG &DAG) const { in LowerReturn()
283 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
284 *DAG.getContext()); in LowerReturn()
307 Val = DAG.getBitcast(VA.getLocVT(), Val); in LowerReturn()
310 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
313 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp165 LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
168 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); in LowerOperation()
169 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
170 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
171 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
172 case ISD::BR_JT: return LowerBR_JT(Op, DAG); in LowerOperation()
173 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
174 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
175 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation()
176 case ISD::VASTART: return LowerVASTART(Op, DAG); in LowerOperation()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp51 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { in numBitsUnsigned() argument
52 return DAG.computeKnownBits(Op).countMaxActiveBits(); in numBitsUnsigned()
55 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { in numBitsSigned() argument
58 return DAG.ComputeMaxSignificantBits(Op); in numBitsSigned()
872 const SelectionDAG &DAG, in isLoadBitCastBeneficial() argument
887 return allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(), in isLoadBitCastBeneficial()
928 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, in getNegatedExpression() argument
944 SDValue NegSrc = getNegatedExpression(Src, DAG, LegalOperations, in getNegatedExpression()
947 return DAG.getNode(AMDGPUISD::RCP, SL, VT, NegSrc, Op->getFlags()); in getNegatedExpression()
954 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression()
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H A DGCNSchedStrategy.cpp78 void GCNSchedStrategy::initialize(ScheduleDAGMI *DAG) { in initialize() argument
79 GenericScheduler::initialize(DAG); in initialize()
81 MF = &DAG->MF; in initialize()
169 ScheduleDAGMI *DAG, const SIRegisterInfo *SRI) { in getRegisterPressures() argument
208 if (!DAG->isTrackingPressure()) in initCandidate()
227 DownwardTracker, UpwardTracker, DAG, SRI); in initCandidate()
234 for (const auto &Diff : DAG->getPressureDiff(SU)) { in initCandidate()
246 DownwardTracker, UpwardTracker, DAG, SRI); in initCandidate()
333 if (DAG->isTrackingPressure()) { in pickNodeFromQueue()
357 TryCand.initResourceDelta(Zone.DAG, SchedModel); in pickNodeFromQueue()
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H A DSIISelLowering.h48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
64 SDValue getPreloadedValue(SelectionDAG &DAG,
70 SelectionDAG &DAG) const override;
71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
74 SelectionDAG &DAG, bool WithChain) const;
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H A DR600ISelLowering.cpp400 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
401 MachineFunction &MF = DAG.getMachineFunction(); in LowerOperation()
404 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
405 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
406 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
409 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); in LowerOperation()
410 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()
411 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW); in LowerOperation()
413 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
414 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h69 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
82 const SelectionDAG &DAG,
87 const SelectionDAG &DAG,
130 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
156 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
390 SelectionDAG &DAG) const override;
393 preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
497 bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const;
516 SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable,
563 const SDLoc &DL, SelectionDAG &DAG,
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H A DAArch64ISelLowering.cpp240 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType() argument
241 assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && in isPackedVectorType()
351 extractPtrauthBlendDiscriminators(SDValue Disc, SelectionDAG *DAG) { in extractPtrauthBlendDiscriminators() argument
372 return std::make_tuple(DAG->getTargetConstant(0, DL, MVT::i64), Disc); in extractPtrauthBlendDiscriminators()
377 AddrDisc = DAG->getRegister(AArch64::NoRegister, MVT::i64); in extractPtrauthBlendDiscriminators()
380 DAG->getTargetConstant(ConstDiscN->getZExtValue(), DL, MVT::i64), in extractPtrauthBlendDiscriminators()
2485 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0), in optimizeLogicalImm()
2486 TLO.DAG.getConstant(NewImm, DL, VT)); in optimizeLogicalImm()
2491 SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT); in optimizeLogicalImm()
2493 TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0); in optimizeLogicalImm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp34 static SDValue createMemMemNode(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in createMemMemNode() argument
37 SDVTList VTs = Op == SystemZISD::CLC ? DAG.getVTList(MVT::i32, MVT::Other) in createMemMemNode()
38 : DAG.getVTList(MVT::Other); in createMemMemNode()
44 return DAG.getNode(Op, DL, VTs, Ops); in createMemMemNode()
51 static SDValue emitMemMemImm(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemImm() argument
56 SDValue LenAdj = DAG.getConstant(Size - Adj, DL, Dst.getValueType()); in emitMemMemImm()
57 return createMemMemNode(DAG, DL, Op, Chain, Dst, Src, LenAdj, Byte); in emitMemMemImm()
60 static SDValue emitMemMemReg(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemReg() argument
64 SDValue LenAdj = DAG.getNode(ISD::ADD, DL, MVT::i64, in emitMemMemReg()
65 DAG.getZExtOrTrunc(Size, DL, MVT::i64), in emitMemMemReg()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp167 SelectionDAG &DAG) const { in LowerOperation()
170 return LowerMUL(Op, DAG); in LowerOperation()
172 return LowerBR_CC(Op, DAG); in LowerOperation()
174 return LowerConstantPool(Op, DAG); in LowerOperation()
176 return LowerGlobalAddress(Op, DAG); in LowerOperation()
178 return LowerBlockAddress(Op, DAG); in LowerOperation()
180 return LowerJumpTable(Op, DAG); in LowerOperation()
182 return LowerSELECT_CC(Op, DAG); in LowerOperation()
184 return LowerSETCC(Op, DAG); in LowerOperation()
186 return LowerSHL_PARTS(Op, DAG); in LowerOperation()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp60 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, in isInTailCallPosition() argument
62 const Function &F = DAG.getMachineFunction().getFunction(); in isInTailCallPosition()
154 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, in makeLibCall() argument
160 InChain = DAG.getEntryNode(); in makeLibCall()
172 : Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); in makeLibCall()
189 DAG.getExternalSymbol(LibcallName, getPointerTy(DAG.getDataLayout())); in makeLibCall()
191 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); in makeLibCall()
192 TargetLowering::CallLoweringInfo CLI(DAG); in makeLibCall()
305 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, in softenSetCCOperands() argument
311 return softenSetCCOperands(DAG, VT, NewLHS, NewRHS, CCCode, dl, OldLHS, in softenSetCCOperands()
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H A DSelectionDAGBuilder.cpp153 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
165 getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, in getCopyFromParts() argument
171 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in getCopyFromParts()
172 if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts, in getCopyFromParts()
177 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
193 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
196 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts()
199 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, PartVT, HalfVT, V, in getCopyFromParts()
201 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, RoundParts / 2, in getCopyFromParts()
204 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
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H A DLegalizeIntegerTypes.cpp42 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG)); in PromoteIntegerResult()
55 N->dump(&DAG); dbgs() << "\n"; in PromoteIntegerResult()
376 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
383 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
388 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0()
407 DAG.getAtomicLoad(ExtType, SDLoc(N), N->getMemoryVT(), ResVT, in PromoteIntRes_Atomic0()
418 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), in PromoteIntRes_Atomic1()
433 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); in PromoteIntRes_AtomicCmpSwap()
440 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other); in PromoteIntRes_AtomicCmpSwap()
441 SDValue Res = DAG.getAtomicCmpSwap( in PromoteIntRes_AtomicCmpSwap()
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H A DLegalizeTypesGeneric.cpp42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
63 auto &DL = DAG.getDataLayout(); in ExpandRes_BITCAST()
69 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
75 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
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H A DLegalizeDAG.cpp90 SelectionDAG &DAG; member in __anon2068f58e0111::SelectionDAGLegalize
100 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSetCCResultType()
106 SelectionDAGLegalize(SelectionDAG &DAG, in SelectionDAGLegalize() argument
109 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG), in SelectionDAGLegalize()
224 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
225 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
230 DAG.ReplaceAllUsesWith(Old, New); in ReplaceNode()
237 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
238 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
240 DAG.ReplaceAllUsesWith(Old, New); in ReplaceNode()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h326 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
332 SelectionDAG &DAG) const override;
381 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
388 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, in getAddrLocal() argument
391 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
392 getTargetNode(N, Ty, DAG, GOTFlag)); in getAddrLocal()
394 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, in getAddrLocal()
395 MachinePointerInfo::getGOT(DAG.getMachineFunction())); in getAddrLocal()
397 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
398 getTargetNode(N, Ty, DAG, LoFlag)); in getAddrLocal()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2741 SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, in emitStackGuardXorFP() argument
2743 EVT PtrTy = getPointerTy(DAG.getDataLayout()); in emitStackGuardXorFP()
2745 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val); in emitStackGuardXorFP()
2895 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { in getReturnAddressFrameIndex()
2896 MachineFunction &MF = DAG.getMachineFunction(); in getReturnAddressFrameIndex()
2910 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout())); in getReturnAddressFrameIndex()
2985 SelectionDAG &DAG) { in TranslateX86CC() argument
2990 RHS = DAG.getConstant(0, DL, RHS.getValueType()); in TranslateX86CC()
3003 RHS = DAG.getConstant(0, DL, RHS.getValueType()); in TranslateX86CC()
3441 const SelectionDAG &DAG, in isLoadBitCastBeneficial() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp253 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn()
255 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
256 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
264 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn_32()
265 MachineFunction &MF = DAG.getMachineFunction(); in LowerReturn_32()
271 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_32()
272 *DAG.getContext()); in LowerReturn_32()
296 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
298 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout()))); in LowerReturn_32()
299 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp267 SelectionDAG &DAG, const SDLoc &DL) { in CreateCopyOfByValArgument() argument
268 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32); in CreateCopyOfByValArgument()
270 return DAG.getMemcpy( in CreateCopyOfByValArgument()
384 M68kTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { in getReturnAddressFrameIndex()
385 MachineFunction &MF = DAG.getMachineFunction(); in getReturnAddressFrameIndex()
397 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout())); in getReturnAddressFrameIndex()
400 SDValue M68kTargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, in EmitTailCallLoadRetAddr() argument
405 EVT VT = getPointerTy(DAG.getDataLayout()); in EmitTailCallLoadRetAddr()
406 OutRetAddr = getReturnAddressFrameIndex(DAG); in EmitTailCallLoadRetAddr()
409 OutRetAddr = DAG.getLoad(VT, DL, Chain, OutRetAddr, MachinePointerInfo()); in EmitTailCallLoadRetAddr()
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h61 SelectionDAG &DAG) const override;
137 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
139 SelectionDAG &DAG) const override;
150 const SelectionDAG &DAG,
154 const SelectionDAG &DAG,
165 const SelectionDAG &DAG,
192 SelectionDAG &DAG) const override;
253 preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N, in preferredShiftLegalizationStrategy() argument
255 if (DAG.getMachineFunction().getFunction().hasMinSize()) in preferredShiftLegalizationStrategy()
257 return TargetLowering::preferredShiftLegalizationStrategy(DAG, N, in preferredShiftLegalizationStrategy()
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H A DRISCVISelLowering.cpp2228 SelectionDAG &DAG) const { in shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()
2434 ISD::CondCode &CC, SelectionDAG &DAG, in translateSetCCForBranch() argument
2455 LHS = DAG.getNode(ISD::SHL, DL, LHS.getValueType(), LHS, in translateSetCCForBranch()
2456 DAG.getConstant(ShAmt, DL, LHS.getValueType())); in translateSetCCForBranch()
2468 RHS = DAG.getConstant(0, DL, RHS.getValueType()); in translateSetCCForBranch()
2475 RHS = DAG.getSignedConstant(C + 1, DL, RHS.getValueType()); in translateSetCCForBranch()
2484 LHS = DAG.getConstant(0, DL, RHS.getValueType()); in translateSetCCForBranch()
2494 RHS = DAG.getSignedConstant(C + 1, DL, RHS.getValueType()); in translateSetCCForBranch()
2858 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT, in getContainerForFixedLengthVector() argument
2860 return getContainerForFixedLengthVector(DAG.getTargetLoweringInfo(), VT, in getContainerForFixedLengthVector()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp320 SelectionDAG &DAG) const { in LowerAsmOperandForConstraint()
327 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); in LowerAsmOperandForConstraint()
430 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const { in LowerFormalArguments() argument
431 MachineFunction &MF = DAG.getMachineFunction(); in LowerFormalArguments()
440 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, in LowerFormalArguments()
441 *DAG.getContext()); in LowerFormalArguments()
468 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Reg, RegVT); in LowerFormalArguments()
480 ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, in LowerFormalArguments()
481 DAG.getValueType(VA.getValVT())); in LowerFormalArguments()
482 ArgValue = DAG.getNode((VA.getValVT() == MVT::f32) ? ISD::BITCAST in LowerFormalArguments()
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/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h628 SelectionDAG &DAG);
633 SelectionDAG &DAG);
638 SelectionDAG &DAG);
643 unsigned ShuffleKind, SelectionDAG &DAG);
648 unsigned ShuffleKind, SelectionDAG &DAG);
653 unsigned ShuffleKind, SelectionDAG &DAG);
683 SelectionDAG &DAG);
704 SelectionDAG &DAG);
710 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
841 SDValue getNegatedExpression(SDValue Op, SelectionDAG &DAG, bool LegalOps,
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