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Searched refs:DAG (Results 1 – 25 of 245) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h143 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG& DAG) const;
179 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
181 SelectionDAG &DAG) const override;
183 SelectionDAG &DAG) const override;
187 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
188 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
189 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
190 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
191 SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
192 SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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H A DHexagonISelLoweringHVX.cpp69 // nodes, which would be unoptimizable by the DAG combiner. in initializeHVXLowering()
499 const SDLoc &dl, SelectionDAG &DAG) const { in getInt()
501 IntOps.push_back(DAG.getConstant(IntId, dl, MVT::i32)); in getInt()
503 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, ResTy, IntOps); in getInt()
540 SelectionDAG &DAG) const { in opCastElem()
544 return DAG.getBitcast(CastTy, Vec); in opCastElem()
549 SelectionDAG &DAG) const { in opJoin()
550 return DAG.getNode(ISD::CONCAT_VECTORS, dl, typeJoin(ty(Ops)), in opJoin()
556 SelectionDAG &DAG) const { in opSplit()
560 return DAG in opSplit()
3488 SelectionDAG &DAG = DCI.DAG; combineTruncateBeforeLegal() local
3528 SelectionDAG &DAG = DCI.DAG; combineConcatVectorsBeforeLegal() local
3588 SelectionDAG &DAG = DCI.DAG; PerformHvxDAGCombine() local
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H A DHexagonISelLowering.cpp164 HexagonTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) in LowerINTRINSIC_WO_CHAIN()
176 SelectionDAG &DAG, const SDLoc &dl) { in CreateCopyOfByValArgument() argument
177 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32); in CreateCopyOfByValArgument()
178 return DAG.getMemcpy( in CreateCopyOfByValArgument()
205 const SDLoc &dl, SelectionDAG &DAG) const { in LowerReturn()
210 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn()
211 *DAG.getContext()); in LowerReturn()
234 Val = DAG.getBitcast(VA.getLocVT(), Val); in LowerReturn()
237 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
240 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
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/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp193 LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
196 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); in LowerOperation()
197 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); in LowerOperation()
198 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); in LowerOperation()
199 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); in LowerOperation()
200 case ISD::BR_JT: return LowerBR_JT(Op, DAG); in LowerOperation()
201 case ISD::LOAD: return LowerLOAD(Op, DAG); in LowerOperation()
202 case ISD::STORE: return LowerSTORE(Op, DAG); in LowerOperation()
203 case ISD::VAARG: return LowerVAARG(Op, DAG); in LowerOperation()
204 case ISD::VASTART: return LowerVASTART(Op, DAG); in LowerOperation()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUISelLowering.cpp51 unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) { in numBitsUnsigned() argument
52 return DAG.computeKnownBits(Op).countMaxActiveBits(); in numBitsUnsigned()
55 unsigned AMDGPUTargetLowering::numBitsSigned(SDValue Op, SelectionDAG &DAG) { in numBitsSigned() argument
58 return DAG.ComputeMaxSignificantBits(Op); in numBitsSigned()
857 const SelectionDAG &DAG, in isLoadBitCastBeneficial() argument
872 return allowsMemoryAccessForAlignment(*DAG.getContext(), DAG.getDataLayout(), in isLoadBitCastBeneficial()
909 SDValue Op, SelectionDAG &DAG, bool LegalOperations, bool ForCodeSize, in getNegatedExpression() argument
925 SDValue NegSrc = getNegatedExpression(Src, DAG, LegalOperations, in getNegatedExpression()
928 return DAG.getNode(AMDGPUISD::RCP, SL, VT, NegSrc, Op->getFlags()); in getNegatedExpression()
935 return TargetLowering::getNegatedExpression(Op, DAG, LegalOperations, in getNegatedExpression()
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H A DGCNSchedStrategy.cpp67 void GCNSchedStrategy::initialize(ScheduleDAGMI *DAG) { in initialize() argument
68 GenericScheduler::initialize(DAG); in initialize()
70 MF = &DAG->MF; in initialize()
173 if (!DAG->isTrackingPressure()) in initCandidate()
198 for (const auto &Diff : DAG->getPressureDiff(SU)) { in initCandidate()
296 if (DAG->isTrackingPressure()) { in pickNodeFromQueue()
312 TryCand.initResourceDelta(Zone.DAG, SchedModel); in pickNodeFromQueue()
346 pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), BotCand, in pickNodeBidirectional()
355 pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), TCand, in pickNodeBidirectional()
368 pickNodeFromQueue(Top, TopPolicy, DAG->getTopRPTracker(), TopCand, in pickNodeBidirectional()
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H A DR600ISelLowering.cpp396 SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { in LowerOperation()
397 MachineFunction &MF = DAG.getMachineFunction(); in LowerOperation()
400 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG); in LowerOperation()
401 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); in LowerOperation()
402 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); in LowerOperation()
405 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); in LowerOperation()
406 case ISD::UADDO: return LowerUADDSUBO(Op, DAG, ISD::ADD, AMDGPUISD::CARRY); in LowerOperation()
407 case ISD::USUBO: return LowerUADDSUBO(Op, DAG, ISD::SUB, AMDGPUISD::BORROW); in LowerOperation()
409 case ISD::FSIN: return LowerTrig(Op, DAG); in LowerOperation()
410 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); in LowerOperation()
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H A DSIISelLowering.h48 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
50 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
51 SDValue getLDSKernelId(SelectionDAG &DAG, const SDLoc &SL) const;
52 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
57 SDValue loadImplicitKernelArgument(SelectionDAG &DAG, MVT VT, const SDLoc &DL,
61 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
64 SDValue getPreloadedValue(SelectionDAG &DAG,
70 SelectionDAG &DAG) const override;
71 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
74 SelectionDAG &DAG, bool WithChain) const;
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H A DAMDGPUISelLowering.h35 SDValue getFFBX_U32(SelectionDAG &DAG, SDValue Op, const SDLoc &DL, unsigned Opc) const;
41 static unsigned numBitsUnsigned(SDValue Op, SelectionDAG &DAG);
46 static unsigned numBitsSigned(SDValue Op, SelectionDAG &DAG);
49 SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFREM(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFCEIL(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFTRUNC(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerFRINT(SDValue Op, SelectionDAG &DAG) const;
58 SDValue LowerFNEARBYINT(SDValue Op, SelectionDAG &DAG) const;
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp24 static SDValue createMemMemNode(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in createMemMemNode() argument
27 SDVTList VTs = Op == SystemZISD::CLC ? DAG.getVTList(MVT::i32, MVT::Other) in createMemMemNode()
28 : DAG.getVTList(MVT::Other); in createMemMemNode()
34 return DAG.getNode(Op, DL, VTs, Ops); in createMemMemNode()
41 static SDValue emitMemMemImm(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemImm() argument
46 SDValue LenAdj = DAG.getConstant(Size - Adj, DL, Dst.getValueType()); in emitMemMemImm()
47 return createMemMemNode(DAG, DL, Op, Chain, Dst, Src, LenAdj, Byte); in emitMemMemImm()
50 static SDValue emitMemMemReg(SelectionDAG &DAG, const SDLoc &DL, unsigned Op, in emitMemMemReg() argument
54 SDValue LenAdj = DAG.getNode(ISD::ADD, DL, MVT::i64, in emitMemMemReg()
55 DAG.getZExtOrTrunc(Size, DL, MVT::i64), in emitMemMemReg()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp53 bool TargetLowering::isInTailCallPosition(SelectionDAG &DAG, SDNode *Node, in isInTailCallPosition() argument
55 const Function &F = DAG.getMachineFunction().getFunction(); in isInTailCallPosition()
146 TargetLowering::makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, in makeLibCall() argument
152 InChain = DAG.getEntryNode(); in makeLibCall()
161 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); in makeLibCall()
175 SDValue Callee = DAG.getExternalSymbol(getLibcallName(LC), in makeLibCall()
176 getPointerTy(DAG.getDataLayout())); in makeLibCall()
178 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); in makeLibCall()
179 TargetLowering::CallLoweringInfo CLI(DAG); in makeLibCall()
291 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT, in softenSetCCOperands() argument
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H A DLegalizeIntegerTypes.cpp42 LLVM_DEBUG(dbgs() << "Promote integer result: "; N->dump(&DAG)); in PromoteIntegerResult()
55 N->dump(&DAG); dbgs() << "\n"; in PromoteIntegerResult()
356 return DAG.getNode(ISD::AssertSext, SDLoc(N), in PromoteIntRes_AssertSext()
363 return DAG.getNode(ISD::AssertZext, SDLoc(N), in PromoteIntRes_AssertZext()
368 EVT ResVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); in PromoteIntRes_Atomic0()
369 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), in PromoteIntRes_Atomic0()
401 SDValue Res = DAG.getAtomic(N->getOpcode(), SDLoc(N), in PromoteIntRes_Atomic1()
416 EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(1)); in PromoteIntRes_AtomicCmpSwap()
423 SDVTList VTs = DAG.getVTList(N->getValueType(0), SVT, MVT::Other); in PromoteIntRes_AtomicCmpSwap()
424 SDValue Res = DAG.getAtomicCmpSwap( in PromoteIntRes_AtomicCmpSwap()
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H A DSelectionDAGBuilder.cpp157 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
169 getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, in getCopyFromParts() argument
175 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); in getCopyFromParts()
176 if (SDValue Val = TLI.joinRegisterPartsIntoValue(DAG, DL, Parts, NumParts, in getCopyFromParts()
181 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT, V, in getCopyFromParts()
197 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); in getCopyFromParts()
200 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); in getCopyFromParts()
203 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, PartVT, HalfVT, V, in getCopyFromParts()
205 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, RoundParts / 2, in getCopyFromParts()
208 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); in getCopyFromParts()
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H A DLegalizeDAG.cpp90 SelectionDAG &DAG; member in __anon2068f58e0111::SelectionDAGLegalize
100 return TLI.getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); in getSetCCResultType()
106 SelectionDAGLegalize(SelectionDAG &DAG, in SelectionDAGLegalize() argument
109 : TM(DAG.getTarget()), TLI(DAG.getTargetLoweringInfo()), DAG(DAG), in SelectionDAGLegalize()
214 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
215 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
220 DAG.ReplaceAllUsesWith(Old, New); in ReplaceNode()
227 LLVM_DEBUG(dbgs() << " ... replacing: "; Old->dump(&DAG); in ReplaceNode()
228 dbgs() << " with: "; New->dump(&DAG)); in ReplaceNode()
230 DAG.ReplaceAllUsesWith(Old, New); in ReplaceNode()
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H A DLegalizeTypesGeneric.cpp42 EVT NOutVT = TLI.getTypeToTransformTo(*DAG.getContext(), OutVT); in ExpandRes_BITCAST()
58 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
59 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
63 auto &DL = DAG.getDataLayout(); in ExpandRes_BITCAST()
69 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
70 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
75 if (TLI.hasBigEndianPartOrdering(OutVT, DAG.getDataLayout())) in ExpandRes_BITCAST()
77 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
78 Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); in ExpandRes_BITCAST()
83 Lo = DAG in ExpandRes_BITCAST()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp174 SelectionDAG &DAG) const { in LowerOperation()
177 return LowerMUL(Op, DAG); in LowerOperation()
179 return LowerBR_CC(Op, DAG); in LowerOperation()
181 return LowerConstantPool(Op, DAG); in LowerOperation()
183 return LowerGlobalAddress(Op, DAG); in LowerOperation()
185 return LowerBlockAddress(Op, DAG); in LowerOperation()
187 return LowerJumpTable(Op, DAG); in LowerOperation()
189 return LowerSELECT_CC(Op, DAG); in LowerOperation()
191 return LowerSETCC(Op, DAG); in LowerOperation()
193 return LowerSHL_PARTS(Op, DAG); in LowerOperation()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp249 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn()
251 return LowerReturn_64(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
252 return LowerReturn_32(Chain, CallConv, IsVarArg, Outs, OutVals, DL, DAG); in LowerReturn()
260 const SDLoc &DL, SelectionDAG &DAG) const { in LowerReturn_32()
261 MachineFunction &MF = DAG.getMachineFunction(); in LowerReturn_32()
267 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs, in LowerReturn_32()
268 *DAG.getContext()); in LowerReturn_32()
292 SDValue Part0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
294 DAG.getConstant(0, DL, getVectorIdxTy(DAG.getDataLayout()))); in LowerReturn_32()
295 SDValue Part1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, in LowerReturn_32()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.h566 bool isReassocProfitable(SelectionDAG &DAG, SDValue N0,
579 const SelectionDAG &DAG,
584 const SelectionDAG &DAG,
614 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
642 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
883 SelectionDAG &DAG) const override;
886 preferredShiftLegalizationStrategy(SelectionDAG &DAG, SDNode *N,
986 bool isAllActivePredicate(SelectionDAG &DAG, SDValue N) const;
1000 SDValue changeStreamingMode(SelectionDAG &DAG, SDLoc DL, bool Enable,
1050 const SDLoc &DL, SelectionDAG &DAG,
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H A DAArch64SelectionDAGInfo.cpp25 SelectionDAG &DAG, const SDLoc &DL, in EmitMOPS() argument
55 MachineFunction &MF = DAG.getMachineFunction(); in EmitMOPS()
66 SrcOrValue = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, SrcOrValue); in EmitMOPS()
69 MachineSDNode *Node = DAG.getMachineNode(MachineOpcode, DL, ResultTys, Ops); in EmitMOPS()
70 DAG.setNodeMemRefs(Node, {DstOp}); in EmitMOPS()
75 MachineSDNode *Node = DAG.getMachineNode(MachineOpcode, DL, ResultTys, Ops); in EmitMOPS()
80 DAG.setNodeMemRefs(Node, {DstOp, SrcOp}); in EmitMOPS()
86 SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dst, SDValue Src, in EmitStreamingCompatibleMemLibCall() argument
89 DAG.getMachineFunction().getSubtarget<AArch64Subtarget>(); in EmitStreamingCompatibleMemLibCall()
93 DstEntry.Ty = PointerType::getUnqual(*DAG.getContext()); in EmitStreamingCompatibleMemLibCall()
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H A DAArch64ISelLowering.cpp234 static inline bool isPackedVectorType(EVT VT, SelectionDAG &DAG) { in isPackedVectorType() argument
235 assert(VT.isVector() && DAG.getTargetLoweringInfo().isTypeLegal(VT) && in isPackedVectorType()
343 extractPtrauthBlendDiscriminators(SDValue Disc, SelectionDAG *DAG) { in extractPtrauthBlendDiscriminators() argument
364 return std::make_tuple(DAG->getTargetConstant(0, DL, MVT::i64), Disc); in extractPtrauthBlendDiscriminators()
369 AddrDisc = DAG->getRegister(AArch64::NoRegister, MVT::i64); in extractPtrauthBlendDiscriminators()
372 DAG->getTargetConstant(ConstDiscN->getZExtValue(), DL, MVT::i64), in extractPtrauthBlendDiscriminators()
2248 New = TLO.DAG.getNode(Op.getOpcode(), DL, VT, Op.getOperand(0), in optimizeLogicalImm()
2249 TLO.DAG.getConstant(NewImm, DL, VT)); in optimizeLogicalImm()
2254 SDValue EncConst = TLO.DAG.getTargetConstant(Enc, DL, VT); in optimizeLogicalImm()
2256 TLO.DAG.getMachineNode(NewOpc, DL, VT, Op.getOperand(0), EncConst), 0); in optimizeLogicalImm()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.h324 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
330 SelectionDAG &DAG) const override;
377 SDValue getGlobalReg(SelectionDAG &DAG, EVT Ty) const;
384 SDValue getAddrLocal(NodeTy *N, const SDLoc &DL, EVT Ty, SelectionDAG &DAG, in getAddrLocal() argument
387 SDValue GOT = DAG.getNode(MipsISD::Wrapper, DL, Ty, getGlobalReg(DAG, Ty), in getAddrLocal()
388 getTargetNode(N, Ty, DAG, GOTFlag)); in getAddrLocal()
390 DAG.getLoad(Ty, DL, DAG.getEntryNode(), GOT, in getAddrLocal()
391 MachinePointerInfo::getGOT(DAG.getMachineFunction())); in getAddrLocal()
393 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal()
394 getTargetNode(N, Ty, DAG, LoFlag)); in getAddrLocal()
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/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp265 SelectionDAG &DAG, const SDLoc &DL) { in CreateCopyOfByValArgument() argument
266 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32); in CreateCopyOfByValArgument()
268 return DAG.getMemcpy( in CreateCopyOfByValArgument()
382 M68kTargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { in getReturnAddressFrameIndex()
383 MachineFunction &MF = DAG.getMachineFunction(); in getReturnAddressFrameIndex()
395 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout())); in getReturnAddressFrameIndex()
398 SDValue M68kTargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, in EmitTailCallLoadRetAddr() argument
403 EVT VT = getPointerTy(DAG.getDataLayout()); in EmitTailCallLoadRetAddr()
404 OutRetAddr = getReturnAddressFrameIndex(DAG); in EmitTailCallLoadRetAddr()
407 OutRetAddr = DAG.getLoad(VT, DL, Chain, OutRetAddr, MachinePointerInfo()); in EmitTailCallLoadRetAddr()
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H A DM68kISelLowering.h1 //===-- M68kISelLowering.h - M68k DAG Lowering Interface --------*- C++ -*-===//
11 /// selection DAG.
30 /// M68k Specific DAG nodes
137 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
151 SelectionDAG &DAG) const override;
168 SelectionDAG &DAG) const override;
195 SelectionDAG &DAG) const;
206 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
210 SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
216 SDValue EmitTailCallStoreRetAddr(SelectionDAG &DAG, MachineFunctio
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2605 SDValue X86TargetLowering::emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, in emitStackGuardXorFP() argument
2607 EVT PtrTy = getPointerTy(DAG.getDataLayout()); in emitStackGuardXorFP()
2609 MachineSDNode *Node = DAG.getMachineNode(XorOp, DL, PtrTy, Val); in emitStackGuardXorFP()
2750 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { in getReturnAddressFrameIndex()
2751 MachineFunction &MF = DAG.getMachineFunction(); in getReturnAddressFrameIndex()
2765 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy(DAG.getDataLayout())); in getReturnAddressFrameIndex()
2840 SelectionDAG &DAG) { in TranslateX86CC() argument
2845 RHS = DAG.getConstant(0, DL, RHS.getValueType()); in TranslateX86CC()
2858 RHS = DAG.getConstant(0, DL, RHS.getValueType()); in TranslateX86CC()
3260 const SelectionDAG &DAG, in isLoadBitCastBeneficial() argument
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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp2030 SelectionDAG &DAG) const { in shouldProduceAndByConstByHoistingConstFromShiftsLHSOfAnd()
2387 ISD::CondCode &CC, SelectionDAG &DAG) { in translateSetCCForBranch() argument
2405 LHS = DAG.getNode(ISD::SHL, DL, LHS.getValueType(), LHS, in translateSetCCForBranch()
2406 DAG.getConstant(ShAmt, DL, LHS.getValueType())); in translateSetCCForBranch()
2418 RHS = DAG.getConstant(0, DL, RHS.getValueType()); in translateSetCCForBranch()
2427 LHS = DAG.getConstant(0, DL, RHS.getValueType()); in translateSetCCForBranch()
2716 static MVT getContainerForFixedLengthVector(SelectionDAG &DAG, MVT VT, in getContainerForFixedLengthVector() argument
2718 return getContainerForFixedLengthVector(DAG.getTargetLoweringInfo(), VT, in getContainerForFixedLengthVector()
2727 static SDValue convertToScalableVector(EVT VT, SDValue V, SelectionDAG &DAG, in convertToScalableVector() argument
2734 SDValue Zero = DAG.getVectorIdxConstant(0, DL); in convertToScalableVector()
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