Home
last modified time | relevance | path

Searched refs:CreateReg (Results 1 – 25 of 77) sorted by relevance

1234

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h69 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
77 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
85 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertReadWriteCSR.cpp107 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in INITIALIZE_PASS()
164 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in emitWriteRoundingMode()
H A DRISCVInsertWriteVXRM.cpp384 MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false, in emitWriteVXRM()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp640 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in addStackMapLiveVars()
688 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
808 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); in selectPatchpoint()
857 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
863 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
876 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
882 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, in selectPatchpoint()
910 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
912 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), in selectXRayCustomEvent()
929 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayTypedEvent()
[all …]
H A DFunctionLoweringInfo.cpp371 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { in CreateReg() function in FunctionLoweringInfo
392 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
H A DInstrEmitter.cpp748 return MachineOperand::CreateReg( in GetMOForConstDbgOp()
836 MOs.push_back(MachineOperand::CreateReg( in EmitDbgInstrRef()
1226 MachineOperand MO = MachineOperand::CreateReg(VReg, /*isDef=*/false, in EmitMachineNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp212 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
219 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixVGPRCopies.cpp64 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTOCRegDeps.cpp120 MI.addOperand(MachineOperand::CreateReg(TOCReg, in processBlock()
H A DPPCPreEmitPeephole.cpp339 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
341 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp217 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
247 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
H A DARMBaseInstrInfo.h565 MachineOperand::CreateReg(PredReg, false)}};
571 return MachineOperand::CreateReg(CCReg, false);
578 return MachineOperand::CreateReg(ARM::CPSR,
H A DARMSLSHardening.cpp354 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertIndirectCallToIndirectJump()
H A DThumb2InstrInfo.cpp603 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
635 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp271 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
282 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
293 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
402 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegKill()
418 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
H A DMachineOutliner.cpp961 MachineOperand::CreateReg(I, true, /* isDef = true */ in outline()
967 MachineOperand::CreateReg(I, false, /* isDef = false */ in outline()
H A DMachineInstr.cpp90 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true)); in addImplicitDefUseOperands()
92 addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true)); in addImplicitDefUseOperands()
2053 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
2119 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDead()
2156 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDefined()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp470 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true)); in changeToAddrMode()
473 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h212 Register CreateReg(MVT VT, bool isDivergent = false);
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp200 static std::unique_ptr<MSP430Operand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon2e2431ce0111::MSP430Operand
454 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc)); in ParseOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp599 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon944a62760211::VEOperand
1475 Operands.push_back(VEOperand::CreateReg(Reg1, S1, E1)); in parseOperand()
1476 Operands.push_back(VEOperand::CreateReg(Reg2, S2, E2)); in parseOperand()
1533 Op = VEOperand::CreateReg(Reg, S, E); in parseVEAsmOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp213 static std::unique_ptr<AVROperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon06c44bb20111::AVROperand
415 Operands.push_back(AVROperand::CreateReg(RegNo, T.getLoc(), T.getEndLoc())); in tryParseRegisterOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp85 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
91 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp373 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false));
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp2263 CreateReg(unsigned RegNum, RegKind Kind, SMLoc S, SMLoc E, MCContext &Ctx, in CreateReg() function in __anon730428320111::AArch64Operand
2291 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount, in CreateVectorReg()
3198 Operands.push_back(AArch64Operand::CreateReg( in tryParseSyspXzrPair()
4612 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
4627 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPR64sp0Operand()
4642 Operands.push_back(AArch64Operand::CreateReg( in tryParseZTOperand()
4681 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
4696 Operands.push_back(AArch64Operand::CreateReg( in tryParseGPROperand()
6292 Operands[2] = AArch64Operand::CreateReg( in MatchAndEmitInstruction()
6455 Operands[2] = AArch64Operand::CreateReg(Reg, RegKind::Scalar, in MatchAndEmitInstruction()
[all …]

1234