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Searched refs:CreateReg (Results 1 – 25 of 80) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrBuilder.h63 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, false, in getFullAddress()
71 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, false, false, in getFullAddress()
79 MO.push_back(MachineOperand::CreateReg(0, false, false, false, false, false, in getFullAddress()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInsertReadWriteCSR.cpp107 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in INITIALIZE_PASS()
164 MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false, in emitWriteRoundingMode()
H A DRISCVInsertVSETVLI.cpp1428 MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false, in emitVSETVLIs()
1476 MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ false, in emitVSETVLIs()
1479 MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ false, in emitVSETVLIs()
1484 MI.addOperand(MachineOperand::CreateReg(RISCV::VL, /*isDef*/ true, in emitVSETVLIs()
1486 MI.addOperand(MachineOperand::CreateReg(RISCV::VTYPE, /*isDef*/ true, in emitVSETVLIs()
H A DRISCVInsertWriteVXRM.cpp408 MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false, in emitWriteVXRM()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp637 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in addStackMapLiveVars()
685 Ops.push_back(MachineOperand::CreateReg( in selectStackmap()
805 Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*isDef=*/true)); in selectPatchpoint()
854 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
860 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/false)); in selectPatchpoint()
873 Ops.push_back(MachineOperand::CreateReg( in selectPatchpoint()
879 Ops.push_back(MachineOperand::CreateReg(Reg, /*isDef=*/true, in selectPatchpoint()
907 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayCustomEvent()
909 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(1)), in selectXRayCustomEvent()
926 Ops.push_back(MachineOperand::CreateReg(getRegForValue(I->getArgOperand(0)), in selectXRayTypedEvent()
[all …]
H A DFunctionLoweringInfo.cpp376 Register FunctionLoweringInfo::CreateReg(MVT VT, bool isDivergent) { in CreateReg() function in FunctionLoweringInfo
397 Register R = CreateReg(RegisterVT, isDivergent); in CreateRegs()
H A DInstrEmitter.cpp744 return MachineOperand::CreateReg( in GetMOForConstDbgOp()
832 MOs.push_back(MachineOperand::CreateReg( in EmitDbgInstrRef()
1227 MachineOperand MO = MachineOperand::CreateReg(VReg, /*isDef=*/false, in EmitMachineNode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonPeephole.cpp201 MI.addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); in runOnMachineFunction()
208 MI.addOperand(MachineOperand::CreateReg( in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTOCRegDeps.cpp110 MI.addOperand(MachineOperand::CreateReg(TOCReg, in processBlock()
H A DPPCPreEmitPeephole.cpp335 MachineOperand::CreateReg(Pair->UseReg, true, true); in addLinkerOpt()
337 MachineOperand::CreateReg(Pair->UseReg, false, true); in addLinkerOpt()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DThumb2ITBlockPass.cpp213 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
243 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, in InsertITInstructions()
H A DARMBaseInstrInfo.h543 MachineOperand::CreateReg(PredReg, false)}};
549 return MachineOperand::CreateReg(CCReg, false);
556 return MachineOperand::CreateReg(ARM::CPSR,
H A DARMSLSHardening.cpp354 BL->addOperand(MachineOperand::CreateReg(Reg, false /*isDef*/, true /*isImp*/, in ConvertIndirectCallToIndirectJump()
H A DThumb2InstrInfo.cpp605 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
637 MI.addOperand(MachineOperand::CreateReg(0, false)); in rewriteT2FrameIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIFixVGPRCopies.cpp80 MachineOperand::CreateReg(AMDGPU::EXEC, false, true)); in run()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveVariables.cpp268 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
279 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
289 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
398 MachineOperand::CreateReg(SubReg, true /*IsDef*/, true /*IsImp*/)); in HandlePhysRegKill()
414 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, in HandlePhysRegKill()
H A DMachineInstr.cpp92 addOperand(MF, MachineOperand::CreateReg(ImpDef, true, true)); in addImplicitDefUseOperands()
94 addOperand(MF, MachineOperand::CreateReg(ImpUse, false, true)); in addImplicitDefUseOperands()
2167 addOperand(MachineOperand::CreateReg(IncomingReg, in addRegisterKilled()
2233 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDead()
2265 addOperand(MachineOperand::CreateReg(Reg, in addRegisterDefined()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCOptAddrMode.cpp470 Ldst.addOperand(MachineOperand::CreateReg(NewBase, true)); in changeToAddrMode()
473 Ldst.addOperand(MachineOperand::CreateReg(BaseReg, false)); in changeToAddrMode()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DFunctionLoweringInfo.h218 Register CreateReg(MVT VT, bool isDivergent = false);
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/AsmParser/
H A DMSP430AsmParser.cpp200 static std::unique_ptr<MSP430Operand> CreateReg(MCRegister Reg, SMLoc S, in CreateReg() function in __anon2e2431ce0111::MSP430Operand
454 Operands.push_back(MSP430Operand::CreateReg(RegNo, StartLoc, EndLoc)); in ParseOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/AsmParser/
H A DVEAsmParser.cpp609 static std::unique_ptr<VEOperand> CreateReg(unsigned RegNum, SMLoc S, in CreateReg() function in __anon944a62760211::VEOperand
1455 Operands.push_back(VEOperand::CreateReg(Reg1, S1, E1)); in parseOperand()
1456 Operands.push_back(VEOperand::CreateReg(Reg2, S2, E2)); in parseOperand()
1513 Op = VEOperand::CreateReg(Reg, S, E); in parseVEAsmOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/AsmParser/
H A DAVRAsmParser.cpp212 static std::unique_ptr<AVROperand> CreateReg(MCRegister Reg, SMLoc S, in CreateReg() function in __anon06c44bb20111::AVROperand
418 Operands.push_back(AVROperand::CreateReg(Reg, T.getLoc(), T.getEndLoc())); in tryParseRegisterOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegStackify.cpp89 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
95 MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, in imposeStackOrdering()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCSEInfo.cpp394 addNodeIDMachineOperand(MachineOperand::CreateReg(Reg, false)); in addNodeIDRegType()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp2630 Operands.push_back(X86Operand::CreateReg(RegNo, Start, End)); in parseIntelOperand()
2827 Operands.push_back(X86Operand::CreateReg(Reg, Loc, EndLoc)); in parseATTOperand()
2952 X86Operand::CreateReg(RegNo, StartLoc, StartLoc)); in HandleAVX512Operand()
3650 Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc); in parseInstruction()
3662 Operands.back() = X86Operand::CreateReg(X86::DX, Op.getStartLoc(), in parseInstruction()
3671 Operands[1] = X86Operand::CreateReg(X86::DX, Op.getStartLoc(), in parseInstruction()
3685 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc), in parseInstruction()
3696 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc)); in parseInstruction()

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