| /freebsd/share/misc/ |
| H A D | pci_vendors | 33 7a00 Hyper Transport Bridge Controller
34 7a02 APB (Advanced Peripheral Bus) Controller
35 7a03 Gigabit Ethernet Controller
36 7a04 OTG USB Controller
38 7a06 DC (Display Controller)
39 7a07 HDA (High Definition Audio) Controller
40 7a08 SATA AHCI Controller
42 7a0b SPI Controller
43 7a0c LPC Controller
44 7a0f DMA (Direct Memory Access) Controller
[all …]
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| /freebsd/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_fdr_logging.cpp | 64 FDRController<> *Controller = nullptr; member
315 if (TLD.Controller != nullptr) in fdrLoggingFlush()
316 TLD.Controller->flush(); in fdrLoggingFlush()
353 if (TLD.Controller != nullptr) in fdrLoggingFlush()
354 TLD.Controller->flush(); in fdrLoggingFlush()
448 if (TLD.Controller != nullptr) { in setupTLD()
449 TLD.Controller->flush(); in setupTLD()
450 TLD.Controller = nullptr; in setupTLD()
456 if (UNLIKELY(TLD.Controller == nullptr)) { in setupTLD()
484 TLD.Controller = CStorage; in setupTLD()
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/ata/ |
| H A D | imx-pata.txt | 1 * Freescale i.MX PATA Controller
5 - reg: Address range of the PATA Controller
6 - interrupts: The interrupt of the PATA Controller
7 - clocks: the clocks for the PATA Controller
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| /freebsd/sys/contrib/device-tree/Bindings/mtd/ |
| H A D | aspeed-smc.txt | 2 * Aspeed SPI Flash Memory Controller
4 The Firmware Memory Controller in the Aspeed AST2500 SoC supports
13 "aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
14 "aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
15 "aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
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| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | aspeed-lpc.txt | 2 Device tree bindings for the Aspeed Low Pin Count (LPC) Bus Controller
8 (typically in a Baseboard Management Controller SoC), but under certain
14 * An IPMI Block Transfer[2] Controller
16 * An LPC Host Controller: Manages LPC functions such as host vs slave mode, the
20 * An LPC Host Interface Controller: Manages functions exposed to the host such
72 LPC Host Interface Controller
75 The LPC Host Interface Controller manages functions exposed to the host such as
110 LPC Host Controller
113 The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
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| H A D | altera-a10sr.txt | 19 a10sr_gpio GPIO Controller
20 a10sr_rst Reset Controller
25 - gpio-controller : Marks the device node as a GPIO Controller.
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| H A D | aspeed-gfx.txt | 1 * Device tree bindings for Aspeed SoC Display Controller (GFX)
3 The Aspeed SoC Display Controller primarily does as its name suggests, but also
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| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | andestech,ativic32.txt | 1 * Andestech Internal Vector Interrupt Controller
3 The Internal Vector Interrupt Controller (IVIC) is a basic interrupt controller
5 bigger External Vector Interrupt Controller.
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| /freebsd/sys/contrib/device-tree/src/arm/broadcom/ |
| H A D | bcm-ns.dtsi | 123 /* PCIe Controller 0 */
131 /* PCIe Controller 1 */
139 /* PCIe Controller 2 */
147 /* USB 2.0 Controller */
150 /* USB 3.0 Controller */
153 /* Ethernet Controller 0 */
156 /* Ethernet Controller 1 */
159 /* Ethernet Controller 2 */
162 /* Ethernet Controller 3 */
165 /* NAND Controller */
[all...] |
| H A D | bcm53573.dtsi | 87 /* PCIe Controller 0 */
95 /* USB 2.0 Controller */
98 /* Ethernet Controller 0 */
104 /* Ethernet Controller 1 */
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | dcsr.txt | 105 Nexus Port Controller
125 The first register range describes the Nexus Port Controller
128 The second register range describes the Nexus Port Controller
166 CoreNet Debug Controller
187 The first register range describes the CoreNet Debug Controller
190 The second register range describes the CoreNet Debug Controller
203 the DPAA Debug Controller. This controller controls debug configuration
232 the OCN Debug Controller.
257 DDR Controller Debug controller
260 the OCN Debug Controller
[all...] |
| H A D | mpc5121-psc.txt | 9 Controller node fsl,mpc5121-psc-fifo is required there:
19 PSC FIFO Controller and b is a field that represents an
42 FIFO Controller
44 PSC FIFO Controller and b is a field that represents an
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| H A D | interlaken-lac.txt | 2 Freescale Interlaken Look-Aside Controller Device Bindings
6 - Interlaken Look-Aside Controller (LAC) Node
8 - Interlaken Look-Aside Controller (LAC) Software Portal Node
9 - Interlaken Look-Aside Controller (LAC) Software Portal Child Nodes
13 Interlaken Look-Aside Controller (LAC) Node
89 Interlaken Look-Aside Controller (LAC) Software Portal Container Node
92 The Interlaken Look-Aside Controller (LAC) utilizes Software Portals to accept
122 Interlaken Look-Aside Controller (LAC) Software Portals Child Nodes
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| /freebsd/sys/contrib/device-tree/Bindings/ufs/ |
| H A D | tc-dwc-g210-pltfrm.txt | 1 * Universal Flash Storage (UFS) DesignWare Host Controller
10 complemented with the Controller IP version:
19 Example for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC:
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| /freebsd/sys/arm64/conf/ |
| H A D | std.rockchip | 12 device dwgpio # Synopsys DesignWare APB GPIO Controller
13 device rk_gpio # RockChip GPIO Controller
14 device rk_pinctrl # RockChip Pinmux Controller
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| H A D | std.marvell | 11 device mvebu_pinctrl # Marvell Pinmux Controller
30 device mv_thermal # Marvell Thermal Sensor Controller
33 device a37x0_spi # Marvell Armada 37x0 SPI Controller
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| H A D | NOTES | 58 device al_iofic # I/O Fabric Interrupt Controller
63 device qcom_gcc # Global Clock Controller
139 device mvebu_pinctrl # Marvell Pinmux Controller
140 device rk_gpio # RockChip GPIO Controller
141 device rk_pinctrl # RockChip Pinmux Controller
175 device aw_thermal # Allwinner Thermal Sensor Controller
176 device mv_thermal # Marvell Thermal Sensor Controller
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| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | hisilicon,hi3660-mailbox.txt | 1 Hisilicon Hi3660 Mailbox Controller
8 Controller
39 Cells must match 'mbox-cells' (See Controller docs above)
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| /freebsd/sys/dev/sdio/ |
| H A D | sdiodevs | 59 product REALTEK RTW8723BS 0xb723 802.11bgn SDIO WLAN with Bluetooth 4.0 Single-Chip Controller
62 product REALTEK RTW8822BS 0xb822 802.11ac/abgn SDIO WLAN with Bluetooth 4.1 Single-Chip Controller
63 product REALTEK RTW8821CS 0xc821 802.11ac/abgn SDIO WLAN with Bluetooth 4.2 Single-Chip Controller
64 product REALTEK RTW8822CS 0xc822 802.11ac/abgn SDIO WLAN with Bluetooth x.x Single-Chip Controller
65 product REALTEK RTW8723DS_1ANT 0xd724 802.11bgn SDIO WLAN with Bluetooth 4.2 Single-Chip Controller
66 product REALTEK RTW8723DS_2ANT 0xd723 802.11bgn SDIO WLAN with Bluetooth 4.2 Single-Chip Controller
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/4xx/ |
| H A D | akebono.txt | 14 1.a) The Secure Digital Host Controller Interface (SDHCI) node
16 Represent the Secure Digital Host Controller Interfaces.
24 1.b) The Advanced Host Controller Interface (AHCI) SATA node
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | marvell,pxa300-gcu.txt | 1 PXA3xx GCU Controller
7 - interrupts : Controller interrupt.
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| /freebsd/sys/contrib/device-tree/Bindings/riscv/ |
| H A D | sifive-l2-cache.txt | 1 SiFive L2 Cache Controller
3 The SiFive Level 2 Cache Controller is used to provide access to fast copies
4 of memory for masters in a Core Complex. The Level 2 Cache Controller also
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | rockchip,dwc3.txt | 8 "ref_clk" Controller reference clk, have to be 24 MHz
9 "suspend_clk" Controller suspend clk, have to be 24 MHz or 32 KHz
12 "grf_clk" Controller grf clk
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | brcm,bus-axi.txt | 33 /* Ethernet Controller 0 */
36 /* Ethernet Controller 1 */
39 /* PCIe Controller 0 */
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| /freebsd/sys/contrib/device-tree/Bindings/fsi/ |
| H A D | ibm,p9-occ.txt | 1 Device-tree bindings for FSI-attached POWER9/POWER10 On-Chip Controller (OCC)
4 This is the binding for the P9 or P10 On-Chip Controller accessed over FSI from
|