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Searched refs:CondReg (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp760 Register &CondReg = CondRegs[Cond]; in getCondOrInverseInReg() local
762 if (!CondReg && !InvCondReg) in getCondOrInverseInReg()
763 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond); in getCondOrInverseInReg()
765 if (CondReg) in getCondOrInverseInReg()
766 return {CondReg, false}; in getCondOrInverseInReg()
790 Register &CondReg = CondRegs[Cond]; in rewriteSetCC() local
791 if (!CondReg) in rewriteSetCC()
792 CondReg = promoteCondToReg(MBB, Pos, Loc, Cond); in rewriteSetCC()
806 Use.getOperand(2).setReg(CondReg); in rewriteSetCC()
826 MRI->replaceRegWith(OldReg, CondReg); in rewriteSetCC()
[all …]
H A DX86FastISel.cpp2117 Register CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2118 if (!CondReg) in X86FastEmitCMoveSelect()
2122 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { in X86FastEmitCMoveSelect()
2123 Register KCondReg = CondReg; in X86FastEmitCMoveSelect()
2124 CondReg = createResultReg(&X86::GR32RegClass); in X86FastEmitCMoveSelect()
2126 TII.get(TargetOpcode::COPY), CondReg) in X86FastEmitCMoveSelect()
2128 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); in X86FastEmitCMoveSelect()
2131 .addReg(CondReg) in X86FastEmitCMoveSelect()
2318 Register CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
2319 if (!CondReg) in X86FastEmitPseudoSelect()
[all …]
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp92 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
107 if (A->modifiesRegister(CondReg, TRI)) { in optimizeVccBranch()
108 if (!A->definesRegister(CondReg, TRI) || in optimizeVccBranch()
113 ReadsCond |= A->readsRegister(CondReg, TRI); in optimizeVccBranch()
150 if (A->getOpcode() == And && SReg == CondReg && !ModifiesExec && in optimizeVccBranch()
177 if (!MI.killsRegister(CondReg, TRI)) { in optimizeVccBranch()
180 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
183 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
240 MI.removeOperand(MI.findRegisterUseOperandIdx(CondReg, TRI, false /*Kill*/)); in optimizeVccBranch()
H A DSIOptimizeExecMaskingPreRA.cpp40 MCRegister CondReg; member in __anon314e3b690111::SIOptimizeExecMaskingPreRA
140 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS); in optimizeVcndVcmpPair()
242 (CmpReg == Register(CondReg) && in optimizeVcndVcmpPair()
245 return MI.readsRegister(CondReg, TRI); in optimizeVcndVcmpPair()
380 CondReg = MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC); in run()
H A DSIInstrInfo.cpp3210 static void preserveCondRegFlags(MachineOperand &CondReg, in preserveCondRegFlags() argument
3212 CondReg.setIsUndef(OrigCond.isUndef()); in preserveCondRegFlags()
3213 CondReg.setIsKill(OrigCond.isKill()); in preserveCondRegFlags()
3258 MachineOperand &CondReg = CondBr->getOperand(1); in insertBranch() local
3259 CondReg.setIsUndef(Cond[1].isUndef()); in insertBranch()
3260 CondReg.setIsKill(Cond[1].isKill()); in insertBranch()
6586 Register CondReg; in emitLoadScalarOpsFromVGPRLoop() local
6606 if (!CondReg) // First. in emitLoadScalarOpsFromVGPRLoop()
6607 CondReg = NewCondReg; in emitLoadScalarOpsFromVGPRLoop()
6611 .addReg(CondReg) in emitLoadScalarOpsFromVGPRLoop()
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H A DAMDGPURegisterBankInfo.cpp861 Register CondReg; in executeInWaterfallLoop() local
921 if (!CondReg) { in executeInWaterfallLoop()
922 CondReg = CmpReg; in executeInWaterfallLoop()
924 CondReg = B.buildAnd(S1, CondReg, CmpReg).getReg(0); in executeInWaterfallLoop()
925 MRI.setRegBank(CondReg, AMDGPU::VCCRegBank); in executeInWaterfallLoop()
937 CondReg = B.buildIntrinsic(Intrinsic::amdgcn_ballot, in executeInWaterfallLoop()
939 .addReg(CondReg) in executeInWaterfallLoop()
941 MRI.setRegClass(CondReg, WaveRC); in executeInWaterfallLoop()
946 .addReg(CondReg, RegState::Kill); in executeInWaterfallLoop()
948 MRI.setSimpleHint(NewExec, CondReg); in executeInWaterfallLoop()
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H A DAMDGPUInstructionSelector.cpp3023 Register CondReg = CondOp.getReg(); in selectG_BRCOND() local
3035 if (!isVCC(CondReg, *MRI)) { in selectG_BRCOND()
3036 if (MRI->getType(CondReg) != LLT::scalar(32)) in selectG_BRCOND()
3047 if (!isVCmpResult(CondReg, *MRI)) { in selectG_BRCOND()
3054 .addReg(CondReg) in selectG_BRCOND()
3057 CondReg = TmpReg; in selectG_BRCOND()
3065 if (!MRI->getRegClassOrNull(CondReg)) in selectG_BRCOND()
3066 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
3069 .addReg(CondReg); in selectG_BRCOND()
H A DAMDGPUISelDAGToDAG.cpp2600 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND() local
2628 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond); in SelectBRCOND()
H A DVOP3Instructions.td1449 class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat<
1453 (i1 CondReg)),
H A DSIISelLowering.cpp4693 Register CondReg = MRI.createVirtualRegister(BoolRC); in emitLoadM0FromVGPRLoop() local
4712 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg) in emitLoadM0FromVGPRLoop()
4721 .addReg(CondReg, RegState::Kill); in emitLoadM0FromVGPRLoop()
4723 MRI.setSimpleHint(NewExec, CondReg); in emitLoadM0FromVGPRLoop()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp922 unsigned CondReg = in selectSelect() local
924 if (CondReg == 0) in selectSelect()
980 .addReg(CondReg); in selectSelect()
1330 unsigned CondReg = getRegForI1Value(Br->getCondition(), Br->getParent(), Not); in selectBr() local
1331 if (CondReg == 0) in selectBr()
1340 .addReg(CondReg); in selectBr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp973 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
974 if (CondReg == 0) in selectBranch()
977 ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true); in selectBranch()
1052 Register CondReg = getRegForValue(Cond); in selectSelect() local
1054 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1061 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true)) in selectSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp776 auto CondReg = MIB.getReg(1); in selectSelect() local
777 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) && in selectSelect()
780 .addUse(CondReg) in selectSelect()
H A DARMFastISel.cpp1665 Register CondReg = getRegForValue(I->getOperand(0)); in SelectSelect() local
1666 if (!CondReg) in SelectSelect()
1695 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); in SelectSelect()
1698 .addReg(CondReg) in SelectSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2474 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2475 if (!CondReg) in selectBranch()
2488 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2489 if (!CondReg) in selectBranch()
2501 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2714 Register CondReg = getRegForValue(Cond); in selectSelect() local
2715 if (!CondReg) in selectSelect()
2763 Register CondReg = getRegForValue(Cond); in selectSelect() local
2764 if (!CondReg) in selectSelect()
2768 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp612 static void getOperandsForBranch(Register CondReg, RISCVCC::CondCode &CC, in getOperandsForBranch() argument
617 if (!mi_match(CondReg, MRI, m_GICmp(m_Pred(Pred), m_Reg(LHS), m_Reg(RHS)))) { in getOperandsForBranch()
618 LHS = CondReg; in getOperandsForBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp773 Register CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
776 CondReg, PPCPred)) in SelectBranch()
781 .addReg(CondReg) in SelectBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp1533 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
1538 .addReg(CondReg) in selectCondBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1824 Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch() local
1825 MachineInstr *CCMI = MRI.getVRegDef(CondReg); in selectCompareBranch()
1838 emitTestBit(CondReg, /*Bit = */ 0, /*IsNegative = */ true, in selectCompareBranch()
1846 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
3549 const Register CondReg = Sel.getCondReg(); in select() local
3559 auto TstMI = MIB.buildInstr(AArch64::ANDSWri, {DeadVReg}, {CondReg}) in select()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp6241 auto [DstReg, DstTy, CondReg, CondTy] = MI.getFirst2RegLLTs(); in moreElementsVector()
6249 auto ShufSplat = MIRBuilder.buildShuffleSplat(MoreTy, CondReg); in moreElementsVector()
6933 Register CondReg = MI.getOperand(1).getReg(); in narrowScalarSelect() local
6934 LLT CondTy = MRI.getType(CondReg); in narrowScalarSelect()
6956 CondReg, Src1Regs[I], Src2Regs[I]); in narrowScalarSelect()
6962 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); in narrowScalarSelect()