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Searched refs:CondReg (Results 1 – 22 of 22) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp753 unsigned &CondReg = CondRegs[Cond]; in getCondOrInverseInReg() local
755 if (!CondReg && !InvCondReg) in getCondOrInverseInReg()
756 CondReg = promoteCondToReg(TestMBB, TestPos, TestLoc, Cond); in getCondOrInverseInReg()
758 if (CondReg) in getCondOrInverseInReg()
759 return {CondReg, false}; in getCondOrInverseInReg()
783 unsigned &CondReg = CondRegs[Cond]; in rewriteSetCC() local
784 if (!CondReg) in rewriteSetCC()
785 CondReg = promoteCondToReg(MBB, Pos, Loc, Cond); in rewriteSetCC()
796 MRI->replaceRegWith(OldReg, CondReg); in rewriteSetCC()
808 MIB.addReg(CondReg); in rewriteSetCC()
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H A DX86FastISel.cpp2111 Register CondReg = getRegForValue(Cond); in X86FastEmitCMoveSelect() local
2112 if (CondReg == 0) in X86FastEmitCMoveSelect()
2116 if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { in X86FastEmitCMoveSelect()
2117 unsigned KCondReg = CondReg; in X86FastEmitCMoveSelect()
2118 CondReg = createResultReg(&X86::GR32RegClass); in X86FastEmitCMoveSelect()
2120 TII.get(TargetOpcode::COPY), CondReg) in X86FastEmitCMoveSelect()
2122 CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); in X86FastEmitCMoveSelect()
2125 .addReg(CondReg) in X86FastEmitCMoveSelect()
2312 Register CondReg = getRegForValue(Cond); in X86FastEmitPseudoSelect() local
2313 if (CondReg == 0) in X86FastEmitPseudoSelect()
[all …]
H A DX86InstructionSelector.cpp
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIPreEmitPeephole.cpp90 const unsigned CondReg = TRI->getVCC(); in optimizeVccBranch() local
105 if (A->modifiesRegister(CondReg, TRI)) { in optimizeVccBranch()
106 if (!A->definesRegister(CondReg, TRI) || in optimizeVccBranch()
111 ReadsCond |= A->readsRegister(CondReg, TRI); in optimizeVccBranch()
148 if (A->getOpcode() == And && SReg == CondReg && !ModifiesExec && in optimizeVccBranch()
175 if (!MI.killsRegister(CondReg, TRI)) { in optimizeVccBranch()
178 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
181 BuildMI(*A->getParent(), *A, A->getDebugLoc(), TII->get(Mov), CondReg) in optimizeVccBranch()
238 MI.removeOperand(MI.findRegisterUseOperandIdx(CondReg, TRI, false /*Kill*/)); in optimizeVccBranch()
H A DSIOptimizeExecMaskingPreRA.cpp39 MCRegister CondReg; member in __anon314e3b690111::SIOptimizeExecMaskingPreRA
132 TRI->findReachingDef(CondReg, AMDGPU::NoSubRegister, *I, *MRI, LIS); in optimizeVcndVcmpPair()
234 (CmpReg == Register(CondReg) && in optimizeVcndVcmpPair()
237 return MI.readsRegister(CondReg, TRI); in optimizeVcndVcmpPair()
359 CondReg = MCRegister::from(Wave32 ? AMDGPU::VCC_LO : AMDGPU::VCC); in runOnMachineFunction()
H A DSIInstrInfo.cpp3142 static void preserveCondRegFlags(MachineOperand &CondReg, in preserveCondRegFlags() argument
3144 CondReg.setIsUndef(OrigCond.isUndef()); in preserveCondRegFlags()
3145 CondReg.setIsKill(OrigCond.isKill()); in preserveCondRegFlags()
3197 MachineOperand &CondReg = CondBr->getOperand(1); in insertBranch() local
3198 CondReg.setIsUndef(Cond[1].isUndef()); in insertBranch()
3199 CondReg.setIsKill(Cond[1].isKill()); in insertBranch()
6281 Register CondReg; in emitLoadScalarOpsFromVGPRLoop() local
6301 if (!CondReg) // First. in emitLoadScalarOpsFromVGPRLoop()
6302 CondReg = NewCondReg; in emitLoadScalarOpsFromVGPRLoop()
6306 .addReg(CondReg) in emitLoadScalarOpsFromVGPRLoop()
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H A DAMDGPURegisterBankInfo.cpp861 Register CondReg; in executeInWaterfallLoop() local
921 if (!CondReg) { in executeInWaterfallLoop()
922 CondReg = CmpReg; in executeInWaterfallLoop()
924 CondReg = B.buildAnd(S1, CondReg, CmpReg).getReg(0); in executeInWaterfallLoop()
925 MRI.setRegBank(CondReg, AMDGPU::VCCRegBank); in executeInWaterfallLoop()
937 CondReg = B.buildIntrinsic(Intrinsic::amdgcn_ballot, in executeInWaterfallLoop()
939 .addReg(CondReg) in executeInWaterfallLoop()
941 MRI.setRegClass(CondReg, WaveRC); in executeInWaterfallLoop()
946 .addReg(CondReg, RegState::Kill); in executeInWaterfallLoop()
948 MRI.setSimpleHint(NewExec, CondReg); in executeInWaterfallLoop()
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H A DAMDGPUInstructionSelector.cpp2829 Register CondReg = CondOp.getReg(); in selectG_BRCOND() local
2841 if (!isVCC(CondReg, *MRI)) { in selectG_BRCOND()
2842 if (MRI->getType(CondReg) != LLT::scalar(32)) in selectG_BRCOND()
2853 if (!isVCmpResult(CondReg, *MRI)) { in selectG_BRCOND()
2860 .addReg(CondReg) in selectG_BRCOND()
2863 CondReg = TmpReg; in selectG_BRCOND()
2871 if (!MRI->getRegClassOrNull(CondReg)) in selectG_BRCOND()
2872 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
2875 .addReg(CondReg); in selectG_BRCOND()
H A DAMDGPUMachineCFGStructurizer.cpp1846 Register CondReg = Cond[0].getReg(); in ensureCondIsNotKilled() local
1847 for (MachineOperand &MO : MRI->use_operands(CondReg)) in ensureCondIsNotKilled()
H A DVOP3Instructions.td902 class DivFmasPat<ValueType vt, Instruction inst, Register CondReg> : GCNPat<
906 (i1 CondReg)),
H A DAMDGPUISelDAGToDAG.cpp2484 Register CondReg = UseSCCBr ? AMDGPU::SCC : TRI->getVCC(); in SelectBRCOND() local
2511 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, CondReg, Cond); in SelectBRCOND()
H A DSIISelLowering.cpp4476 Register CondReg = MRI.createVirtualRegister(BoolRC); in emitLoadM0FromVGPRLoop() local
4495 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg) in emitLoadM0FromVGPRLoop()
4503 .addReg(CondReg, RegState::Kill); in emitLoadM0FromVGPRLoop()
4505 MRI.setSimpleHint(NewExec, CondReg); in emitLoadM0FromVGPRLoop()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp916 unsigned CondReg = in selectSelect() local
918 if (CondReg == 0) in selectSelect()
974 .addReg(CondReg); in selectSelect()
1321 unsigned CondReg = getRegForI1Value(Br->getCondition(), Br->getParent(), Not); in selectBr() local
1322 if (CondReg == 0) in selectBr()
1331 .addReg(CondReg); in selectBr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp961 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
962 if (CondReg == 0) in selectBranch()
965 ZExtCondReg = emitIntExt(MVT::i1, CondReg, MVT::i32, true); in selectBranch()
1040 Register CondReg = getRegForValue(Cond); in selectSelect() local
1042 if (!Src1Reg || !Src2Reg || !CondReg) in selectSelect()
1049 if (!emitIntExt(MVT::i1, CondReg, MVT::i32, ZExtCondReg, true)) in selectSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp776 auto CondReg = MIB.getReg(1); in selectSelect() local
777 assert(validReg(MRI, CondReg, 1, ARM::GPRRegBankID) && in selectSelect()
780 .addUse(CondReg) in selectSelect()
H A DARMFastISel.cpp1610 Register CondReg = getRegForValue(I->getOperand(0)); in SelectSelect() local
1611 if (CondReg == 0) return false; in SelectSelect()
1637 CondReg = constrainOperandRegClass(TII.get(TstOpc), CondReg, 0); in SelectSelect()
1640 .addReg(CondReg) in SelectSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp2476 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2477 if (!CondReg) in selectBranch()
2490 Register CondReg = getRegForValue(BI->getCondition()); in selectBranch() local
2491 if (CondReg == 0) in selectBranch()
2503 = constrainOperandRegClass(II, CondReg, II.getNumDefs()); in selectBranch()
2716 Register CondReg = getRegForValue(Cond); in selectSelect() local
2717 if (!CondReg) in selectSelect()
2765 Register CondReg = getRegForValue(Cond); in selectSelect() local
2766 if (!CondReg) in selectSelect()
2770 CondReg = constrainOperandRegClass(II, CondReg, 1); in selectSelect()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp444 static void getOperandsForBranch(Register CondReg, MachineRegisterInfo &MRI, in getOperandsForBranch() argument
449 if (!mi_match(CondReg, MRI, m_GICmp(m_Pred(Pred), m_Reg(LHS), m_Reg(RHS)))) { in getOperandsForBranch()
450 LHS = CondReg; in getOperandsForBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp785 Register CondReg = createResultReg(&PPC::CRRCRegClass); in SelectBranch() local
788 CondReg, PPCPred)) in SelectBranch()
793 .addReg(CondReg) in SelectBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp1493 const Register CondReg = I.getOperand(0).getReg(); in selectCondBranch() local
1498 .addReg(CondReg) in selectCondBranch()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp1816 Register CondReg = I.getOperand(0).getReg(); in selectCompareBranch() local
1817 MachineInstr *CCMI = MRI.getVRegDef(CondReg); in selectCompareBranch()
1830 emitTestBit(CondReg, /*Bit = */ 0, /*IsNegative = */ true, in selectCompareBranch()
1838 MIB.buildInstr(AArch64::ANDSWri, {LLT::scalar(32)}, {CondReg}).addImm(1); in selectCompareBranch()
3414 const Register CondReg = Sel.getCondReg(); in select() local
3424 auto TstMI = MIB.buildInstr(AArch64::ANDSWri, {DeadVReg}, {CondReg}) in select()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp5547 auto [DstReg, DstTy, CondReg, CondTy] = MI.getFirst2RegLLTs(); in moreElementsVector()
5555 auto ShufSplat = MIRBuilder.buildShuffleSplat(MoreTy, CondReg); in moreElementsVector()
6243 Register CondReg = MI.getOperand(1).getReg(); in narrowScalarSelect() local
6244 LLT CondTy = MRI.getType(CondReg); in narrowScalarSelect()
6266 CondReg, Src1Regs[I], Src2Regs[I]); in narrowScalarSelect()
6272 LeftoverTy, CondReg, Src1LeftoverRegs[I], Src2LeftoverRegs[I]); in narrowScalarSelect()