3142 static void preserveCondRegFlags(MachineOperand &CondReg,  in preserveCondRegFlags()  argument
3144   CondReg.setIsUndef(OrigCond.isUndef());  in preserveCondRegFlags()
3145   CondReg.setIsKill(OrigCond.isKill());  in preserveCondRegFlags()
3197   MachineOperand &CondReg = CondBr->getOperand(1);  in insertBranch()  local
3198   CondReg.setIsUndef(Cond[1].isUndef());  in insertBranch()
3199   CondReg.setIsKill(Cond[1].isKill());  in insertBranch()
6281   Register CondReg;  in emitLoadScalarOpsFromVGPRLoop()  local
6301       if (!CondReg) // First.  in emitLoadScalarOpsFromVGPRLoop()
6302         CondReg = NewCondReg;  in emitLoadScalarOpsFromVGPRLoop()
6306             .addReg(CondReg)  in emitLoadScalarOpsFromVGPRLoop()
6308         CondReg = AndReg;  in emitLoadScalarOpsFromVGPRLoop()
6354         if (!CondReg) // First.  in emitLoadScalarOpsFromVGPRLoop()
6355           CondReg = NewCondReg;  in emitLoadScalarOpsFromVGPRLoop()
6359               .addReg(CondReg)  in emitLoadScalarOpsFromVGPRLoop()
6361           CondReg = AndReg;  in emitLoadScalarOpsFromVGPRLoop()
6384   MRI.setSimpleHint(SaveExec, CondReg);  in emitLoadScalarOpsFromVGPRLoop()
6388       .addReg(CondReg, RegState::Kill);  in emitLoadScalarOpsFromVGPRLoop()
7138     Register CondReg = Inst.getOperand(1).getReg();  in moveToVALUImpl()  local
7139     bool IsSCC = CondReg == AMDGPU::SCC;  in moveToVALUImpl()
7145         .addReg(IsSCC ? VCC : CondReg);  in moveToVALUImpl()
7296     Register CondReg = MRI.createVirtualRegister(RI.getWaveMaskRegClass());  in moveToVALUImpl()  local
7298         BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(NewOpcode), CondReg)  in moveToVALUImpl()
7316     addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg);  in moveToVALUImpl()
7555   Register CondReg = Cond.getReg();  in lowerSelect()  local
7556   bool IsSCC = (CondReg == AMDGPU::SCC);  in lowerSelect()
7564     MRI.replaceRegWith(Dest.getReg(), CondReg);  in lowerSelect()
7568   Register NewCondReg = CondReg;  in lowerSelect()