| /freebsd/contrib/llvm-project/clang/lib/StaticAnalyzer/Checkers/ |
| H A D | IdenticalExprChecker.cpp | 136 const Expr *Cond1 = I->getCond(); in VisitIfStmt() local
140 if (isIdenticalStmt(AC->getASTContext(), Cond1, Cond2, false)) { in VisitIfStmt()
141 SourceRange Sr = Cond1->getSourceRange(); in VisitIfStmt()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | LibCallsShrinkWrap.cpp | 88 auto Cond1 = createCond(BBBuilder, Arg, Cmp, Val); in createOrCond() local
89 return BBBuilder.CreateOr(Cond1, Cond2); in createOrCond()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LICM.cpp | 2416 Value *Cond1, *Cond2; in hoistMinMax() local
2417 if (match(&I, m_LogicalOr(m_Value(Cond1), m_Value(Cond2)))) { in hoistMinMax()
2419 } else if (match(&I, m_LogicalAnd(m_Value(Cond1), m_Value(Cond2)))) { in hoistMinMax()
2444 if (!MatchICmpAgainstInvariant(Cond1, P1, LHS1, RHS1) || in hoistMinMax()
2479 eraseInstruction(*cast<Instruction>(Cond1), SafetyInfo, MSSAU); in hoistMinMax()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 1681 Value *CreateLogicalAnd(Value *Cond1, Value *Cond2, const Twine &Name = "") {
1683 return CreateSelect(Cond1, Cond2,
1687 Value *CreateLogicalOr(Value *Cond1, Value *Cond2, const Twine &Name = "") {
1689 return CreateSelect(Cond1, ConstantInt::getAllOnesValue(Cond2->getType()),
1693 Value *CreateLogicalOp(Instruction::BinaryOps Opc, Value *Cond1, Value *Cond2,
1697 return CreateLogicalAnd(Cond1, Cond2, Name);
1699 return CreateLogicalOr(Cond1, Cond2, Name);
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | IfConversion.cpp | 1785 SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond; in IfConvertDiamondCommon() local
1799 std::swap(Cond1, Cond2); in IfConvertDiamondCommon()
1963 PredicateBlock(*BBI1, MBB1.end(), *Cond1, &RedefsByFalse); in IfConvertDiamondCommon()
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| H A D | CodeGenPrepare.cpp | 8771 Value *Cond1, *Cond2; in splitBranchCondition() local
8773 m_LogicalAnd(m_OneUse(m_Value(Cond1)), m_OneUse(m_Value(Cond2))))) in splitBranchCondition()
8775 else if (match(LogicOp, m_LogicalOr(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
8787 if (!IsGoodCond(Cond1) || !IsGoodCond(Cond2)) in splitBranchCondition()
8801 Br1->setCondition(Cond1); in splitBranchCondition()
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| H A D | ModuloSchedule.cpp | 337 SmallVector<MachineOperand, 4> Cond1; in generateEpilog() local
338 TII->insertBranch(*LastEpilogBB, LoopExitBB, nullptr, Cond1, DebugLoc()); in generateEpilog()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 3397 const APInt *Cond1, Value *CtlzOp, in isSafeToRemoveBitCeilSelect() argument
3420 CmpInst::getInversePredicate(Pred), *Cond1); in isSafeToRemoveBitCeilSelect()
3497 const APInt *Cond1; in foldBitCeil() local
3499 if (!match(SI.getCondition(), m_ICmp(Pred, m_Value(Cond0), m_APInt(Cond1)))) in foldBitCeil()
3514 !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth, in foldBitCeil()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 6126 SDValue Cond1 = N->getOperand(0); in WidenVecRes_Select()
6127 EVT CondVT = Cond1.getValueType(); in WidenVecRes_Select()
6140 Cond1 = GetWidenedVector(Cond1); in WidenVecRes_Select()
6153 if (Cond1.getValueType() != CondWidenVT) in WidenVecRes_Select()
6154 Cond1 = ModifyToType(Cond1, CondWidenVT); in WidenVecRes_Select()
6161 return DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2,
6163 return DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2); in WidenVecRes_SELECT_CC()
6122 SDValue Cond1 = N->getOperand(0); WidenVecRes_Select() local
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| H A D | DAGCombiner.cpp | 11544 SDValue Cond0, Cond1; in foldVSelectToSignBitSplatMask() local
11546 if (!sd_match(N0, m_OneUse(m_SetCC(m_Value(Cond0), m_Value(Cond1), in foldVSelectToSignBitSplatMask()
11553 if (CC == ISD::SETLT && isNullOrNullSplat(Cond1)) in foldVSelectToSignBitSplatMask()
11555 else if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond1)) in foldVSelectToSignBitSplatMask()
11639 SDValue Cond1 = N0->getOperand(1); in visitSELECT() local
11641 DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2, Flags); in visitSELECT()
11652 SDValue Cond1 = N0->getOperand(1); in visitSELECT() local
11654 Cond1, N1, N2, Flags); in visitSELECT()
11704 SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1); in visitSELECT() local
11713 combineMinNumMaxNum(DL, VT, Cond0, Cond1, N1, N2, CC)) in visitSELECT()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 3529 const Value *Cond1 = SI1->getCondition(); in isNonEqualSelect() local
3531 if (Cond1 == Cond2) in isNonEqualSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 46159 SDValue Cond1 = Cond.getOperand(1); in combineSelect() local
46181 if (LHS == Cond0 && RHS == Cond1) { in combineSelect()
46185 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
46190 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
46209 Cond1 == InnerSetCC.getOperand(1)) { in combineSelect()
46221 Cond = DAG.getSetCC(DL, CondVT, Cond0, Cond1, NewCC); in combineSelect()
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