| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/ |
| H A D | LibCallsShrinkWrap.cpp | 88 auto Cond1 = createCond(BBBuilder, Arg, Cmp, Val); in createOrCond() local
89 return BBBuilder.CreateOr(Cond1, Cond2); in createOrCond()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 1730 Value *CreateLogicalAnd(Value *Cond1, Value *Cond2, const Twine &Name = "") {
1732 return CreateSelect(Cond1, Cond2,
1736 Value *CreateLogicalOr(Value *Cond1, Value *Cond2, const Twine &Name = "") {
1738 return CreateSelect(Cond1, ConstantInt::getAllOnesValue(Cond2->getType()),
1742 Value *CreateLogicalOp(Instruction::BinaryOps Opc, Value *Cond1, Value *Cond2,
1746 return CreateLogicalAnd(Cond1, Cond2, Name);
1748 return CreateLogicalOr(Cond1, Cond2, Name);
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | LICM.cpp | 2427 Value *Cond1, *Cond2; in hoistMinMax() local
2428 if (match(&I, m_LogicalOr(m_Value(Cond1), m_Value(Cond2)))) { in hoistMinMax()
2430 } else if (match(&I, m_LogicalAnd(m_Value(Cond1), m_Value(Cond2)))) { in hoistMinMax()
2455 if (!MatchICmpAgainstInvariant(Cond1, P1, LHS1, RHS1) || in hoistMinMax()
2493 Instruction &CondI1 = *cast<Instruction>(Cond1); in hoistMinMax()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | IfConversion.cpp | 1803 SmallVector<MachineOperand, 4> *Cond1 = &BBI.BrCond; in IfConvertDiamondCommon() local
1817 std::swap(Cond1, Cond2); in IfConvertDiamondCommon()
1978 PredicateBlock(*BBI1, MBB1.end(), *Cond1, &RedefsByFalse); in IfConvertDiamondCommon()
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| H A D | CodeGenPrepare.cpp | 9171 Value *Cond1, *Cond2; in splitBranchCondition() local
9173 m_LogicalAnd(m_OneUse(m_Value(Cond1)), m_OneUse(m_Value(Cond2))))) in splitBranchCondition()
9175 else if (match(LogicOp, m_LogicalOr(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
9187 if (!IsGoodCond(Cond1) || !IsGoodCond(Cond2)) in splitBranchCondition()
9201 Br1->setCondition(Cond1); in splitBranchCondition()
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| H A D | ModuloSchedule.cpp | 341 SmallVector<MachineOperand, 4> Cond1; in generateEpilog() local
342 TII->insertBranch(*LastEpilogBB, LoopExitBB, nullptr, Cond1, DebugLoc()); in generateEpilog()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZAsmPrinter.cpp | 939 int64_t Cond1 = MI.getOperand(2).getImm(); in LowerPATCHABLE_RET() local
942 .addImm(Cond1 ^ Cond0) in LowerPATCHABLE_RET()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 3488 const APInt *Cond1, Value *CtlzOp, in isSafeToRemoveBitCeilSelect() argument
3511 CmpInst::getInversePredicate(Pred), *Cond1); in isSafeToRemoveBitCeilSelect()
3590 const APInt *Cond1; in foldBitCeil() local
3592 if (!match(SI.getCondition(), m_ICmp(Pred, m_Value(Cond0), m_APInt(Cond1)))) in foldBitCeil()
3607 !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth, in foldBitCeil()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 6568 SDValue Cond1 = N->getOperand(0); in WidenVecRes_Select() local
6569 EVT CondVT = Cond1.getValueType(); in WidenVecRes_Select()
6582 Cond1 = GetWidenedVector(Cond1); in WidenVecRes_Select()
6595 if (Cond1.getValueType() != CondWidenVT) in WidenVecRes_Select()
6596 Cond1 = ModifyToType(Cond1, CondWidenVT); in WidenVecRes_Select()
6603 return DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2, in WidenVecRes_Select()
6605 return DAG.getNode(Opcode, SDLoc(N), WidenVT, Cond1, InOp1, InOp2); in WidenVecRes_Select()
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| H A D | DAGCombiner.cpp | 12078 SDValue Cond0, Cond1; in foldVSelectToSignBitSplatMask() local
12080 if (!sd_match(N0, m_OneUse(m_SetCC(m_Value(Cond0), m_Value(Cond1), in foldVSelectToSignBitSplatMask()
12087 if (CC == ISD::SETLT && isNullOrNullSplat(Cond1)) in foldVSelectToSignBitSplatMask()
12089 else if (CC == ISD::SETGT && isAllOnesOrAllOnesSplat(Cond1)) in foldVSelectToSignBitSplatMask()
12217 SDValue Cond1 = N0->getOperand(1); in visitSELECT() local
12219 DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond1, N1, N2, Flags); in visitSELECT()
12230 SDValue Cond1 = N0->getOperand(1); in visitSELECT() local
12232 Cond1, N1, N2, Flags); in visitSELECT()
12300 SDValue Cond0 = N0.getOperand(0), Cond1 = N0.getOperand(1); in visitSELECT() local
12309 combineMinNumMaxNum(DL, VT, Cond0, Cond1, N1, N2, CC)) in visitSELECT()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | ValueTracking.cpp | 3759 const Value *Cond1 = SI1->getCondition(); in isNonEqualSelect() local
3761 if (Cond1 == Cond2) in isNonEqualSelect()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 47901 SDValue Cond1 = Cond.getOperand(1); in combineSelect() local
47923 if (LHS == Cond0 && RHS == Cond1) { in combineSelect()
47927 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
47932 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
47951 Cond1 == InnerSetCC.getOperand(1)) { in combineSelect()
47963 Cond = DAG.getSetCC(DL, CondVT, Cond0, Cond1, NewCC); in combineSelect()
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