| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelDAGToDAG.cpp | 4883 MVT CmpVT = N0.getSimpleValueType(); in tryVPTESTM() local
4884 MVT CmpSVT = CmpVT.getVectorElementType(); in tryVPTESTM()
4904 bool Widen = !Subtarget->hasVLX() && !CmpVT.is512BitVector(); in tryVPTESTM()
4962 unsigned Scale = CmpVT.is128BitVector() ? 4 : 2; in tryVPTESTM()
4963 unsigned SubReg = CmpVT.is128BitVector() ? X86::sub_xmm : X86::sub_ymm; in tryVPTESTM()
4964 unsigned NumElts = CmpVT.getVectorNumElements() * Scale; in tryVPTESTM()
4965 CmpVT = MVT::getVectorVT(CmpSVT, NumElts); in tryVPTESTM()
4968 CmpVT), 0); in tryVPTESTM()
4969 Src0 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src0); in tryVPTESTM()
4972 Src1 = CurDAG->getTargetInsertSubreg(SubReg, dl, CmpVT, ImplDef, Src1); in tryVPTESTM()
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| H A D | X86FastISel.cpp | 2072 EVT CmpVT = TLI.getValueType(DL, CmpLHS->getType()); in X86FastEmitCMoveSelect() local
2074 if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc())) in X86FastEmitCMoveSelect()
2308 EVT CmpVT = TLI.getValueType(DL, CmpLHS->getType()); in X86FastEmitPseudoSelect() local
2309 if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc())) in X86FastEmitPseudoSelect()
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| H A D | X86ISelLowering.cpp | 22042 EVT VecVT, EVT CmpVT, bool HasPT, F SToV) { in emitOrXorXorTree() argument
22046 SDValue A = emitOrXorXorTree(Op0, DL, DAG, VecVT, CmpVT, HasPT, SToV); in emitOrXorXorTree()
22047 SDValue B = emitOrXorXorTree(Op1, DL, DAG, VecVT, CmpVT, HasPT, SToV); in emitOrXorXorTree()
22048 if (VecVT != CmpVT) in emitOrXorXorTree()
22049 return DAG.getNode(ISD::OR, DL, CmpVT, A, B); in emitOrXorXorTree()
22052 return DAG.getNode(ISD::AND, DL, CmpVT, A, B); in emitOrXorXorTree()
22057 if (VecVT != CmpVT) in emitOrXorXorTree()
22058 return DAG.getSetCC(DL, CmpVT, A, B, ISD::SETNE); in emitOrXorXorTree()
22061 return DAG.getSetCC(DL, CmpVT, A, B, ISD::SETEQ); in emitOrXorXorTree()
22119 EVT CmpVT = PreferKOT ? MVT::v16i1 : VecVT; in combineVectorSizedSetCCEquality() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6793 EVT CmpVT; in LowerVSETCC() local
6795 CmpVT = Op0.getValueType().changeVectorElementTypeToInteger(); in LowerVSETCC()
6808 CmpVT = VT; in LowerVSETCC()
6815 unsigned CmpElements = CmpVT.getVectorNumElements() * 2; in LowerVSETCC()
6823 Merged = DAG.getNode(ISD::BITCAST, dl, CmpVT, Merged); in LowerVSETCC()
6825 Merged = DAG.getNOT(dl, Merged, CmpVT); in LowerVSETCC()
6830 if (CmpVT.getVectorElementType() == MVT::i64) in LowerVSETCC()
6861 SDValue TmpOp0 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op1, Op0, in LowerVSETCC()
6863 SDValue TmpOp1 = DAG.getNode(ARMISD::VCMP, dl, CmpVT, Op0, Op1, in LowerVSETCC()
6865 SDValue Result = DAG.getNode(ISD::OR, dl, CmpVT, TmpOp0, TmpOp1); in LowerVSETCC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 15079 EVT CmpVT = LHS.getValueType().changeVectorElementTypeToInteger(); in LowerVSETCC() local
15086 EmitVectorComparison(LHS, RHS, AArch64CC, false, CmpVT, dl, DAG); in LowerVSETCC()
15119 CmpVT = MVT::v4i32; in LowerVSETCC()
15136 EmitVectorComparison(LHS, RHS, CC1, NoNaNs, CmpVT, dl, DAG); in LowerVSETCC()
15142 EmitVectorComparison(LHS, RHS, CC2, NoNaNs, CmpVT, dl, DAG); in LowerVSETCC()
15146 Cmp = DAG.getNode(ISD::OR, dl, CmpVT, Cmp, Cmp2); in LowerVSETCC()
19818 EVT CmpVT = InfoAndKind.IsAArch64 in performSetccAddFolding() local
19821 if (CmpVT != MVT::i32 && CmpVT != MVT::i64) in performSetccAddFolding()
19835 ISD::getSetCCInverse(InfoAndKind.Info.Generic.CC, CmpVT), CCVal, DAG, in performSetccAddFolding()
21001 EVT CmpVT = N->getOperand(2).getValueType(); in tryConvertSVEWideCompare() local
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 8165 EVT CmpVT = Op.getOperand(0).getValueType(); in LowerSELECT_CC() local
8173 if (!Subtarget.hasP9Vector() && CmpVT == MVT::f128) { in LowerSELECT_CC()
8175 dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT), in LowerSELECT_CC()
8182 if (!CmpVT.isFloatingPoint() || !TV.getValueType().isFloatingPoint() || in LowerSELECT_CC()
8257 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); in LowerSELECT_CC()
8267 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); in LowerSELECT_CC()
8273 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, Flags); in LowerSELECT_CC()
8279 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); in LowerSELECT_CC()
8285 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, Flags); in LowerSELECT_CC()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 6027 EVT CmpVT = LHS.getValueType(); in lowerICMPIntrinsic() local
6028 if (CmpVT == MVT::i16 && !TLI.isTypeLegal(MVT::i16)) { in lowerICMPIntrinsic()
6057 EVT CmpVT = Src0.getValueType(); in lowerFCMPIntrinsic() local
6060 if (CmpVT == MVT::f16 && !TLI.isTypeLegal(CmpVT)) { in lowerFCMPIntrinsic()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeDAG.cpp | 4180 EVT CmpVT = Tmp1.getValueType(); in ExpandNode() local
4184 EVT CCVT = getSetCCResultType(CmpVT); in ExpandNode()
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| H A D | SelectionDAGBuilder.cpp | 8988 EVT CmpVT = EVT::getIntegerVT(LHS->getContext(), LoadVT.getSizeInBits()); in visitMemCmpBCmpCall() local
8989 LoadL = DAG.getBitcast(CmpVT, LoadL); in visitMemCmpBCmpCall()
8990 LoadR = DAG.getBitcast(CmpVT, LoadR); in visitMemCmpBCmpCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6934 EVT CmpVT = Tmp1.getValueType(); in LowerOperation() local
6936 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), CmpVT); in LowerOperation()
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