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Searched refs:CSR_WRITE_2 (Results 1 – 25 of 39) sorted by relevance

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/freebsd/sys/dev/xl/
H A Dif_xl.c406 CSR_WRITE_2(sc, XL_W4_PHY_MGMT, val); in xl_mii_bitbang_write()
571 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
574 CSR_WRITE_2(sc, XL_W0_EE_CMD, in xl_read_eeprom()
644 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); in xl_rxfilter_90x()
668 CSR_WRITE_2(sc, XL_COMMAND, h | XL_CMD_RX_SET_HASH | XL_HASH_SET); in xl_check_maddr_90xB()
705 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_RX_SET_HASH | i); in xl_rxfilter_90xB()
712 CSR_WRITE_2(sc, XL_COMMAND, rxfilt | XL_CMD_RX_SET_FILT); in xl_rxfilter_90xB()
733 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); in xl_setcfg()
818 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_START); in xl_setmode()
820 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP); in xl_setmode()
[all …]
H A Dif_xlreg.h653 #define CSR_WRITE_2(sc, reg, val) \ macro
671 CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_WINSEL | x); \
/freebsd/sys/dev/vte/
H A Dif_vte.c175 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ | in vte_miibus_readreg()
199 CSR_WRITE_2(sc, VTE_MMWD, val); in vte_miibus_writereg()
200 CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE | in vte_miibus_writereg()
256 CSR_WRITE_2(sc, VTE_MRICR, val); in vte_miibus_statchg()
264 CSR_WRITE_2(sc, VTE_MTICR, val); in vte_miibus_statchg()
1147 CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START); in vte_start_locked()
1243 CSR_WRITE_2(sc, VTE_MCR0, mcr); in vte_mac_config()
1344 CSR_WRITE_2(sc, VTE_MIER, 0); in vte_intr()
1365 CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS); in vte_intr()
1564 CSR_WRITE_2(sc, VTE_MRDCR, prog | in vte_rxeof()
[all …]
H A Dif_vtevar.h149 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd/sys/dev/bwi/
H A Dbwimac.c217 CSR_WRITE_2(sc, data_reg, v); in bwi_memobj_write_2()
230 CSR_WRITE_2(sc, BWI_MOBJ_DATA_UNALIGN, v >> 16); in bwi_memobj_write_4()
234 CSR_WRITE_2(sc, BWI_MOBJ_DATA, v & 0xffff); in bwi_memobj_write_4()
278 CSR_WRITE_2(mac->mac_sc, BWI_BBP_ATTEN, BWI_BBP_ATTEN_MAGIC); in bwi_mac_lateattach()
349 CSR_WRITE_2(sc, BWI_BBP_ATTEN, 0); in bwi_mac_init()
366 CSR_WRITE_2(sc, 0x60e, 0); in bwi_mac_init()
367 CSR_WRITE_2(sc, 0x610, 0x8000); in bwi_mac_init()
368 CSR_WRITE_2(sc, 0x604, 0); in bwi_mac_init()
369 CSR_WRITE_2(sc, 0x606, 0x200); in bwi_mac_init()
393 CSR_WRITE_2(sc, BWI_MAC_POWERUP_DELAY, sc->sc_pwron_delay); in bwi_mac_init()
[all …]
H A Dbwiphy.c139 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl); in bwi_phy_write()
140 CSR_WRITE_2(sc, BWI_PHY_DATA, data); in bwi_phy_write()
148 CSR_WRITE_2(sc, BWI_PHY_CTRL, ctrl); in bwi_phy_read()
441 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT); in bwi_phy_init_11b_rev4()
451 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1); in bwi_phy_init_11b_rev4()
488 CSR_WRITE_2(sc, BWI_RF_CHAN_EX, 0x1100); in bwi_phy_init_11b_rev4()
535 CSR_WRITE_2(sc, BWI_RF_ANTDIV, 0); in bwi_phy_init_11b_rev5()
559 CSR_WRITE_2(sc, BWI_BPHY_CTRL, BWI_BPHY_CTRL_INIT); in bwi_phy_init_11b_rev5()
567 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL1); in bwi_phy_init_11b_rev5()
721 CSR_WRITE_2(sc, BWI_PHY_MAGIC_REG1, BWI_PHY_MAGIC_REG1_VAL2); in bwi_phy_init_11b_rev6()
[all …]
H A Dbwirf.c201 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); in bwi_rf_write()
202 CSR_WRITE_2(sc, BWI_RF_DATA_LO, data); in bwi_rf_write()
220 CSR_WRITE_2(sc, BWI_RF_CTRL, ctrl); in bwi_rf_read()
251 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO); in bwi_rf_attach()
255 CSR_WRITE_2(sc, BWI_RF_CTRL, BWI_RF_CTRL_RFINFO); in bwi_rf_attach()
354 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan)); in bwi_rf_set_chan()
580 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan + 4)); in bwi_rf_work_around()
582 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(1)); in bwi_rf_work_around()
584 CSR_WRITE_2(sc, BWI_RF_CHAN, BWI_RF_2GHZ_CHAN(chan)); in bwi_rf_work_around()
786 CSR_WRITE_2(sc, BWI_BPHY_CTRL, 0x3f3f); in bwi_rf_init_bcm2050()
[all …]
H A Dif_bwivar.h83 #define CSR_WRITE_2(sc, reg, val) \ macro
89 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
94 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
99 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
/freebsd/sys/dev/ste/
H A Dif_ste.c189 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
192 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
296 CSR_WRITE_2(sc, STE_MACCTL0, cfg); in ste_miibus_statchg()
393 CSR_WRITE_2(sc, STE_EEPROM_CTL, STE_EEOPCODE_READ | (off + i)); in ste_read_eeprom()
448 CSR_WRITE_2(sc, STE_MAR0, hashes[0] & 0xFFFF); in ste_rxfilter()
449 CSR_WRITE_2(sc, STE_MAR1, (hashes[0] >> 16) & 0xFFFF); in ste_rxfilter()
450 CSR_WRITE_2(sc, STE_MAR2, hashes[1] & 0xFFFF); in ste_rxfilter()
451 CSR_WRITE_2(sc, STE_MAR3, (hashes[1] >> 16) & 0xFFFF); in ste_rxfilter()
552 CSR_WRITE_2(sc, STE_COUNTDOWN, in ste_intr()
579 CSR_WRITE_2(sc, STE_IMR, intrs); in ste_intr()
[all …]
/freebsd/sys/dev/stge/
H A Dif_stge.c399 CSR_WRITE_2(sc, STGE_EepromCtrl, in stge_read_eeprom()
1304 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_ioctl()
1312 CSR_WRITE_2(sc, STGE_IntEnable, in stge_ioctl()
1501 CSR_WRITE_2(sc, STGE_IntEnable, sc->sc_IntEnable); in stge_intr()
2007 CSR_WRITE_2(sc, STGE_StationAddress0, htole16(eaddr[0])); in stge_init_locked()
2008 CSR_WRITE_2(sc, STGE_StationAddress1, htole16(eaddr[1])); in stge_init_locked()
2009 CSR_WRITE_2(sc, STGE_StationAddress2, htole16(eaddr[2])); in stge_init_locked()
2051 CSR_WRITE_2(sc, STGE_TxStartThresh, sc->sc_txthresh); in stge_init_locked()
2058 CSR_WRITE_2(sc, STGE_RxEarlyThresh, 0x7ff); in stge_init_locked()
2083 CSR_WRITE_2(sc, STGE_IntEnable, 0); in stge_init_locked()
[all …]
/freebsd/sys/dev/vge/
H A Dif_vgevar.h218 #define CSR_WRITE_2(sc, reg, val) \ macro
233 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
240 CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
H A Dif_vge.c405 CSR_WRITE_2(sc, VGE_MIIDATA, data); in vge_miibus_writereg()
1587 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, in vge_rxeof()
1995 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); in vge_start_locked()
2077 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); in vge_init_locked()
2081 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); in vge_init_locked()
2082 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); in vge_init_locked()
2092 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); in vge_init_locked()
2102 CSR_WRITE_2(sc, VGE_TX_PAUSE_TIMER, 0xFFFF); in vge_init_locked()
2404 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); in vge_stop()
/freebsd/sys/dev/vr/
H A Dif_vr.c272 CSR_WRITE_2(sc, VR_MIIDATA, data); in vr_miibus_writereg()
733 CSR_WRITE_2(sc, VR_ISR, 0xFFFF); in vr_attach()
734 CSR_WRITE_2(sc, VR_IMR, 0); in vr_attach()
736 CSR_WRITE_2(sc, VR_MII_IMR, 0); in vr_attach()
1610 CSR_WRITE_2(sc, VR_ISR, status); in vr_poll_locked()
1674 CSR_WRITE_2(sc, VR_IMR, 0x0000); in vr_intr()
1705 CSR_WRITE_2(sc, VR_IMR, 0); in vr_int_task()
1706 CSR_WRITE_2(sc, VR_ISR, status); in vr_int_task()
1711 CSR_WRITE_2(sc, VR_ISR, status); in vr_int_task()
1737 CSR_WRITE_2(sc, VR_IMR, VR_INTRS); in vr_int_task()
[all …]
H A Dif_vrreg.h750 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->vr_res, reg, val) macro
759 #define VR_SETBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
760 #define VR_CLRBIT16(sc, reg, x) CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
/freebsd/sys/dev/rl/
H A Dif_rl.c466 CSR_WRITE_2(sc, rl8139_reg, data); in rl_miibus_writereg()
1205 CSR_WRITE_2(sc, RL_CURRXADDR, cur_rx - 16); in rl_rxeof()
1316 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_OFF_CMD); in rl_twister_update()
1319 CSR_WRITE_2(sc, RL_CSCFG, RL_CSCFG_LINK_DOWN_CMD); in rl_twister_update()
1462 CSR_WRITE_2(sc, RL_ISR, status); in rl_poll_locked()
1501 CSR_WRITE_2(sc, RL_IMR, 0); in rl_intr()
1503 CSR_WRITE_2(sc, RL_ISR, status); in rl_intr()
1527 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_intr()
1738 CSR_WRITE_2(sc, RL_IMR, 0); in rl_init_locked()
1742 CSR_WRITE_2(sc, RL_IMR, RL_INTRS); in rl_init_locked()
[all …]
H A Dif_rlreg.h949 #define CSR_WRITE_2(sc, reg, val) \ macro
971 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) | (val))
974 CSR_WRITE_2(sc, offset, CSR_READ_2(sc, offset) & ~(val))
/freebsd/sys/dev/re/
H A Dif_re.c612 CSR_WRITE_2(sc, re8139_reg, data); in re_miibus_writereg()
822 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); in re_diag()
839 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); in re_diag()
851 CSR_WRITE_2(sc, RL_ISR, status); in re_diag()
2539 CSR_WRITE_2(sc, RL_ISR, status); in re_poll_locked()
2568 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr()
2589 CSR_WRITE_2(sc, RL_ISR, status); in re_int_task()
2642 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); in re_int_task()
2663 CSR_WRITE_2(sc, RL_IMR, 0); in re_intr_msi()
2671 CSR_WRITE_2(sc, RL_ISR, status); in re_intr_msi()
[all …]
/freebsd/sys/dev/msk/
H A Dif_msk.c686 CSR_WRITE_2(sc_if->msk_softc, in msk_rx_fill()
751 CSR_WRITE_2(sc_if->msk_softc, in msk_init_rx_ring()
819 CSR_WRITE_2(sc_if->msk_softc, in msk_init_jumbo_rx_ring()
1293 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); in msk_phy_power()
1307 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), in msk_phy_power()
1309 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), in msk_phy_power()
1366 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); in mskc_reset()
1370 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); in mskc_reset()
1375 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); in mskc_reset()
1376 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); in mskc_reset()
[all …]
/freebsd/sys/dev/fxp/
H A Dif_fxp.c1122 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
1124 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); in fxp_eeprom_shiftin()
1126 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_shiftin()
1144 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, FXP_EEPROM_EECS); in fxp_eeprom_getword()
1158 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1160 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); in fxp_eeprom_getword()
1162 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1177 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg | FXP_EEPROM_EESK); in fxp_eeprom_getword()
1181 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, reg); in fxp_eeprom_getword()
1184 CSR_WRITE_2(sc, FXP_CSR_EEPROMCONTROL, 0); in fxp_eeprom_getword()
[all …]
H A Dif_fxpvar.h248 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->fxp_res[0], reg, val) macro
/freebsd/sys/dev/ipw/
H A Dif_ipwreg.h338 #define CSR_WRITE_2(sc, reg, val) \ macro
366 CSR_WRITE_2((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/freebsd/sys/dev/iwi/
H A Dif_iwireg.h588 #define CSR_WRITE_2(sc, reg, val) \ macro
608 CSR_WRITE_2((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/freebsd/sys/dev/sk/
H A Dif_sk.c412 CSR_WRITE_2(sc, SK_WIN_BASE + SK_REG(reg), val); in sk_win_write_2()
414 CSR_WRITE_2(sc, reg, val); in sk_win_write_2()
1162 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_RESET); in sk_reset()
1163 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_RESET); in sk_reset()
1165 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_SET); in sk_reset()
1168 CSR_WRITE_2(sc, SK_CSR, SK_CSR_SW_UNRESET); in sk_reset()
1170 CSR_WRITE_2(sc, SK_CSR, SK_CSR_MASTER_UNRESET); in sk_reset()
1172 CSR_WRITE_2(sc, SK_LINK_CTRL, SK_LINK_RESET_CLEAR); in sk_reset()
1719 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_ON); in skc_attach()
2476 CSR_WRITE_2(sc, SK_LED, SK_LED_GREEN_OFF); in skc_shutdown()
/freebsd/sys/dev/ale/
H A Dif_alevar.h230 #define CSR_WRITE_2(_sc, reg, val) \ macro
/freebsd/sys/dev/age/
H A Dif_agevar.h238 #define CSR_WRITE_2(_sc, reg, val) \ macro

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