175 	CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_READ |  in vte_miibus_readreg()
199 	CSR_WRITE_2(sc, VTE_MMWD, val);  in vte_miibus_writereg()
200 	CSR_WRITE_2(sc, VTE_MMDIO, MMDIO_WRITE |  in vte_miibus_writereg()
256 		CSR_WRITE_2(sc, VTE_MRICR, val);  in vte_miibus_statchg()
264 		CSR_WRITE_2(sc, VTE_MTICR, val);  in vte_miibus_statchg()
1147 		CSR_WRITE_2(sc, VTE_TX_POLL, TX_POLL_START);  in vte_start_locked()
1243 	CSR_WRITE_2(sc, VTE_MCR0, mcr);  in vte_mac_config()
1344 	CSR_WRITE_2(sc, VTE_MIER, 0);  in vte_intr()
1365 		CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);  in vte_intr()
1564 		CSR_WRITE_2(sc, VTE_MRDCR, prog |  in vte_rxeof()
1597 	CSR_WRITE_2(sc, VTE_MCR1, mcr | MCR1_MAC_RESET);  in vte_reset()
1610 	CSR_WRITE_2(sc, VTE_MACSM, 0x0002);  in vte_reset()
1611 	CSR_WRITE_2(sc, VTE_MACSM, 0);  in vte_reset()
1620 		CSR_WRITE_2(sc, VTE_MDCSC, mdcsc);  in vte_reset()
1676 	CSR_WRITE_2(sc, VTE_MID0L, eaddr[1] << 8 | eaddr[0]);  in vte_init_locked()
1677 	CSR_WRITE_2(sc, VTE_MID0M, eaddr[3] << 8 | eaddr[2]);  in vte_init_locked()
1678 	CSR_WRITE_2(sc, VTE_MID0H, eaddr[5] << 8 | eaddr[4]);  in vte_init_locked()
1682 	CSR_WRITE_2(sc, VTE_MTDSA1, paddr >> 16);  in vte_init_locked()
1683 	CSR_WRITE_2(sc, VTE_MTDSA0, paddr & 0xFFFF);  in vte_init_locked()
1686 	CSR_WRITE_2(sc, VTE_MRDSA1, paddr >> 16);  in vte_init_locked()
1687 	CSR_WRITE_2(sc, VTE_MRDSA0, paddr & 0xFFFF);  in vte_init_locked()
1694 	CSR_WRITE_2(sc, VTE_MRDCR, (VTE_RX_RING_CNT & VTE_MRDCR_RESIDUE_MASK) |  in vte_init_locked()
1707 	CSR_WRITE_2(sc, VTE_MRBSR, VTE_RX_BUF_SIZE_MAX);  in vte_init_locked()
1710 	CSR_WRITE_2(sc, VTE_MBCR, MBCR_FIFO_XFER_LENGTH_16 |  in vte_init_locked()
1721 	CSR_WRITE_2(sc, VTE_MCR0, MCR0_ACCPT_LONG_PKT);  in vte_init_locked()
1728 	CSR_WRITE_2(sc, VTE_MCR1, MCR1_PKT_LENGTH_1537 |  in vte_init_locked()
1735 	CSR_WRITE_2(sc, VTE_MRICR, 0);  in vte_init_locked()
1736 	CSR_WRITE_2(sc, VTE_MTICR, 0);  in vte_init_locked()
1739 	CSR_WRITE_2(sc, VTE_MECIER, VTE_MECIER_INTRS);  in vte_init_locked()
1744 	CSR_WRITE_2(sc, VTE_MIER, VTE_INTRS);  in vte_init_locked()
1745 	CSR_WRITE_2(sc, VTE_MISR, 0);  in vte_init_locked()
1776 	CSR_WRITE_2(sc, VTE_MIER, 0);  in vte_stop()
1777 	CSR_WRITE_2(sc, VTE_MECIER, 0);  in vte_stop()
1831 		CSR_WRITE_2(sc, VTE_MCR0, mcr);  in vte_start_mac()
1857 		CSR_WRITE_2(sc, VTE_MCR0, mcr);  in vte_stop_mac()
2029 	CSR_WRITE_2(sc, VTE_MAR0, ctx.mchash[0]);  in vte_rxfilter()
2030 	CSR_WRITE_2(sc, VTE_MAR1, ctx.mchash[1]);  in vte_rxfilter()
2031 	CSR_WRITE_2(sc, VTE_MAR2, ctx.mchash[2]);  in vte_rxfilter()
2032 	CSR_WRITE_2(sc, VTE_MAR3, ctx.mchash[3]);  in vte_rxfilter()
2035 		CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 0,  in vte_rxfilter()
2037 		CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 2,  in vte_rxfilter()
2039 		CSR_WRITE_2(sc, VTE_RXFILTER_PEEFECT_BASE + 8 * i + 4,  in vte_rxfilter()
2042 	CSR_WRITE_2(sc, VTE_MCR0, mcr);  in vte_rxfilter()