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Searched refs:CSR_WRITE_1 (Results 1 – 25 of 29) sorted by relevance

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/freebsd/sys/dev/vge/
H A Dif_vge.c251 CSR_WRITE_1(sc, VGE_EEADDR, addr); in vge_eeprom_getword()
308 CSR_WRITE_1(sc, VGE_MIICMD, 0); in vge_miipoll_stop()
327 CSR_WRITE_1(sc, VGE_MIICMD, 0); in vge_miipoll_start()
328 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); in vge_miipoll_start()
343 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); in vge_miipoll_start()
369 CSR_WRITE_1(sc, VGE_MIIADDR, reg); in vge_miibus_readreg()
402 CSR_WRITE_1(sc, VGE_MIIADDR, reg); in vge_miibus_writereg()
440 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); in vge_cam_clear()
442 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); in vge_cam_clear()
446 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); in vge_cam_clear()
[all …]
H A Dif_vgevar.h220 #define CSR_WRITE_1(sc, reg, val) \ macro
231 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
238 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd/sys/dev/vr/
H A Dif_vr.c248 CSR_WRITE_1(sc, VR_MIIADDR, reg); in vr_miibus_readreg()
271 CSR_WRITE_1(sc, VR_MIIADDR, reg); in vr_miibus_writereg()
342 CSR_WRITE_1(sc, VR_CR1, cr1); in vr_miibus_statchg()
357 CSR_WRITE_1(sc, VR_FLOWCR1, fc); in vr_miibus_statchg()
365 CSR_WRITE_1(sc, VR_MISC_CR0, fc); in vr_miibus_statchg()
384 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); in vr_cam_mask()
386 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); in vr_cam_mask()
388 CSR_WRITE_1(sc, VR_CAMCTL, 0); in vr_cam_mask()
399 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_MCAST); in vr_cam_data()
401 CSR_WRITE_1(sc, VR_CAMCTL, VR_CAMCTL_ENA | VR_CAMCTL_VLAN); in vr_cam_data()
[all …]
H A Dif_vrreg.h751 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->vr_res, reg, val) macro
756 #define VR_SETBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
757 #define VR_CLRBIT(sc, reg, x) CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
/freebsd/sys/dev/re/
H A Dif_re.c358 CSR_WRITE_1(sc, RL_EECMD, \
362 CSR_WRITE_1(sc, RL_EECMD, \
737 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); in re_reset()
748 CSR_WRITE_1(sc, 0x82, 1); in re_reset()
1323 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); in re_attach()
1326 CSR_WRITE_1(sc, RL_CFG2, cfg); in re_attach()
1327 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); in re_attach()
1360 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); in re_attach()
1365 CSR_WRITE_1(sc, RL_CFG2, cfg); in re_attach()
1367 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); in re_attach()
[all …]
/freebsd/sys/dev/rl/
H A Dif_rl.c264 CSR_WRITE_1(sc, RL_EECMD, \
268 CSR_WRITE_1(sc, RL_EECMD, \
308 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); in rl_eeprom_getword()
315 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_PROGRAM|RL_EE_SEL); in rl_eeprom_getword()
330 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); in rl_eeprom_getword()
382 CSR_WRITE_1(sc, RL_MII, val); in rl_mii_bitbang_write()
568 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); in rl_reset()
1706 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); in rl_init_locked()
1711 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); in rl_init_locked()
1724 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); in rl_init_locked()
[all …]
H A Dif_rlreg.h951 #define CSR_WRITE_1(sc, reg, val) \ macro
965 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) | (val))
968 CSR_WRITE_1(sc, offset, CSR_READ_1(sc, offset) & ~(val))
/freebsd/sys/dev/msk/
H A Dif_msk.c509 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), in msk_miibus_statchg()
1252 CSR_WRITE_1(sc, B0_POWER_CTRL, in msk_phy_power()
1268 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); in msk_phy_power()
1336 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); in msk_phy_power()
1337 CSR_WRITE_1(sc, B0_POWER_CTRL, in msk_phy_power()
1369 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); in mskc_reset()
1381 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); in mskc_reset()
1418 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); in mskc_reset()
1419 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); in mskc_reset()
1438 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); in mskc_reset()
[all …]
H A Dif_mskreg.h2128 #define CSR_WRITE_1(sc, reg, val) \ macro
2164 CSR_WRITE_1((sc_if)->msk_softc, (reg), (val))
/freebsd/sys/dev/ste/
H A Dif_ste.c195 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
198 CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
228 CSR_WRITE_1(sc, STE_PHYCTL, val); in ste_mii_bitbang_write()
452 CSR_WRITE_1(sc, STE_RX_MODE, rxcfg); in ste_rxfilter()
1529 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 64); in ste_init_locked()
1538 CSR_WRITE_1(sc, STE_WAKE_EVENT, val); in ste_init_locked()
1541 CSR_WRITE_1(sc, STE_TX_DMABURST_THRESH, STE_PACKET_SIZE >> 8); in ste_init_locked()
1547 CSR_WRITE_1(sc, STE_TX_RECLAIM_THRESH, (STE_PACKET_SIZE >> 4)); in ste_init_locked()
1564 CSR_WRITE_1(sc, STE_TX_DMAPOLL_PERIOD, 0); in ste_init_locked()
1633 CSR_WRITE_1(sc, STE_RX_DMAPOLL_PERIOD, 0); in ste_stop()
[all …]
H A Dif_stereg.h485 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd/sys/dev/stge/
H A Dif_stge.c273 CSR_WRITE_1(sc, STGE_PhyCtrl, val); in stge_mii_bitbang_write()
985 CSR_WRITE_1(sc, STGE_WakeEvent, v); in stge_setwol()
1028 CSR_WRITE_1(sc, STGE_WakeEvent, v); in stge_resume()
1950 CSR_WRITE_1(sc, STGE_PhySet, v); in stge_reset()
2045 CSR_WRITE_1(sc, STGE_TxDMAPollPeriod, 127); in stge_init_locked()
2048 CSR_WRITE_1(sc, STGE_RxDMAPollPeriod, 1); in stge_init_locked()
2054 CSR_WRITE_1(sc, STGE_RxDMABurstThresh, 0x30); in stge_init_locked()
2055 CSR_WRITE_1(sc, STGE_RxDMAUrgentThresh, 0x30); in stge_init_locked()
2061 CSR_WRITE_1(sc, STGE_TxDMABurstThresh, 0x30); in stge_init_locked()
2062 CSR_WRITE_1(sc, STGE_TxDMAUrgentThresh, 0x04); in stge_init_locked()
[all …]
H A Dif_stgereg.h93 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd/sys/dev/fxp/
H A Dif_fxp.c351 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, FXP_CB_COMMAND_NOP); in fxp_scb_cmd()
354 CSR_WRITE_1(sc, FXP_CSR_SCB_COMMAND, cmd); in fxp_scb_cmd()
492 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); in fxp_attach()
909 CSR_WRITE_1(sc, FXP_CSR_PMDR, CSR_READ_1(sc, FXP_CSR_PMDR)); in fxp_attach()
1007 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); in fxp_detach()
1091 CSR_WRITE_1(sc, FXP_CSR_PMDR, in fxp_resume()
1675 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, tmp); in fxp_poll()
1721 CSR_WRITE_1(sc, FXP_CSR_SCB_STATACK, statack); in fxp_intr()
2180 CSR_WRITE_1(sc, FXP_CSR_SCB_INTRCNTL, FXP_SCB_INTR_DISABLE); in fxp_stop()
2404 CSR_WRITE_1(sc, FXP_CSR_FC_THRESH, 1); in fxp_init_body()
[all …]
H A Dif_fxpvar.h247 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->fxp_res[0], reg, val) macro
/freebsd/sys/dev/ipw/
H A Dif_ipwreg.h335 #define CSR_WRITE_1(sc, reg, val) \ macro
361 CSR_WRITE_1((sc), IPW_CSR_INDIRECT_DATA, (val)); \
/freebsd/sys/dev/xl/
H A Dif_xl.c468 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); in xl_miibus_statchg()
809 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX); in xl_setmode()
813 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, in xl_setmode()
2092 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); in xl_txeoc()
2106 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); in xl_txeoc()
2129 CSR_WRITE_1(sc, XL_TX_STATUS, 0x01); in xl_txeoc()
2701 CSR_WRITE_1(sc, XL_W2_STATION_ADDR_LO + i, in xl_init_locked()
2742 CSR_WRITE_1(sc, XL_TX_FREETHRESH, XL_PACKET_SIZE >> 8); in xl_init_locked()
2782 CSR_WRITE_1(sc, XL_DOWN_POLL, 64); in xl_init_locked()
2815 CSR_WRITE_1(sc, XL_W3_MAC_CTRL, macctl); in xl_init_locked()
H A Dif_xlreg.h655 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd/sys/dev/iwi/
H A Dif_iwireg.h585 #define CSR_WRITE_1(sc, reg, val) \ macro
603 CSR_WRITE_1((sc), IWI_CSR_INDIRECT_DATA, (val)); \
/freebsd/sys/dev/ale/
H A Dif_alevar.h232 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd/sys/dev/alc/
H A Dif_alcvar.h263 #define CSR_WRITE_1(_sc, reg, val) \ macro
/freebsd/sys/dev/my/
H A Dif_myreg.h392 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd/sys/dev/lge/
H A Dif_lgereg.h544 #define CSR_WRITE_1(sc, reg, val) \ macro
/freebsd/sys/dev/netmap/
H A Dif_re_netmap.h141 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); in re_netmap_txsync()
/freebsd/sys/dev/sge/
H A Dif_sge.c182 #define CSR_WRITE_1(cs, reg, val) bus_write_1(sc->sge_res, reg, val) macro
1654 CSR_WRITE_1(sc, RxMacAddr + i, if_getlladdr(ifp)[i]); in sge_init_locked()

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