358 	CSR_WRITE_1(sc, RL_EECMD,			\
362 	CSR_WRITE_1(sc, RL_EECMD,			\
737 	CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET);  in re_reset()
748 		CSR_WRITE_1(sc, 0x82, 1);  in re_reset()
1323 				CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);  in re_attach()
1326 				CSR_WRITE_1(sc, RL_CFG2, cfg);  in re_attach()
1327 				CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);  in re_attach()
1360 		CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);  in re_attach()
1365 			CSR_WRITE_1(sc, RL_CFG2, cfg);  in re_attach()
1367 		CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);  in re_attach()
1558 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);  in re_attach()
1561 	CSR_WRITE_1(sc, sc->rl_cfg1, cfg);  in re_attach()
1564 	CSR_WRITE_1(sc, sc->rl_cfg5, cfg);  in re_attach()
1565 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);  in re_attach()
1613 			CSR_WRITE_1(sc, RL_GPIO,  in re_attach()
1616 			CSR_WRITE_1(sc, RL_GPIO,  in re_attach()
1622 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80);  in re_attach()
1624 			CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08);  in re_attach()
2542 			CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);  in re_poll_locked()
2617 		CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);  in re_int_task()
2709 		CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);  in re_intr_msi()
2947 			CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);  in re_start_locked()
3004 	CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START);  in re_start_tx()
3033 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);  in re_set_jumbo()
3035 		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |  in re_set_jumbo()
3041 			CSR_WRITE_1(sc, sc->rl_cfg4,  in re_set_jumbo()
3045 			CSR_WRITE_1(sc, sc->rl_cfg4,  in re_set_jumbo()
3049 		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &  in re_set_jumbo()
3055 			CSR_WRITE_1(sc, sc->rl_cfg4,  in re_set_jumbo()
3059 			CSR_WRITE_1(sc, sc->rl_cfg4,  in re_set_jumbo()
3063 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);  in re_set_jumbo()
3195 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);  in re_init_locked()
3198 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);  in re_init_locked()
3225 		CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);  in re_init_locked()
3240 	CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16);  in re_init_locked()
3258 		CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB | RL_CMD_RX_ENB);  in re_init_locked()
3345 	CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |  in re_init_locked()
3638 		CSR_WRITE_1(sc, RL_COMMAND, 0x00);  in re_stop()
3640 		CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB |  in re_stop()
3654 		CSR_WRITE_1(sc, RL_COMMAND, 0x00);  in re_stop()
3745 			CSR_WRITE_1(sc, RL_GPIO,  in re_resume()
3873 			CSR_WRITE_1(sc, RL_GPIO,  in re_setwol()
3886 			CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB);  in re_setwol()
3889 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);  in re_setwol()
3896 	CSR_WRITE_1(sc, sc->rl_cfg1, v);  in re_setwol()
3902 	CSR_WRITE_1(sc, sc->rl_cfg3, v);  in re_setwol()
3913 	CSR_WRITE_1(sc, sc->rl_cfg5, v);  in re_setwol()
3916 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);  in re_setwol()
3920 		CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80);  in re_setwol()
3943 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);  in re_clrwol()
3947 	CSR_WRITE_1(sc, sc->rl_cfg3, v);  in re_clrwol()
3950 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);  in re_clrwol()
3955 	CSR_WRITE_1(sc, sc->rl_cfg5, v);  in re_clrwol()