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Searched refs:CSNEG (Results 1 – 16 of 16) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.h321 CSNEG, // Conditional select negate. enumerator
H A DARMScheduleM85.td556 (instregex "t2(CSEL|CSINC|CSINV|CSNEG)")>;
H A DARMISelLowering.cpp1895 MAKE_CASE(ARMISD::CSNEG) in getTargetNodeName()
5561 Opcode = ARMISD::CSNEG; in LowerSELECT_CC()
19019 case ARMISD::CSNEG: in PerformDAGCombine()
20106 case ARMISD::CSNEG: { in computeKnownBitsForTargetNode()
20119 else if (Op.getOpcode() == ARMISD::CSNEG) in computeKnownBitsForTargetNode()
H A DARMInstrInfo.td150 def ARMcsneg : SDNode<"ARMISD::CSNEG", SDT_ARMCSel>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX2T99.td436 "CSNEG(W|X)r")>;
458 "CSNEG(W|X)r")>;
477 "CSNEG(W|X)r")>;
H A DAArch64SchedThunderX3T110.td696 "CSNEG(W|X)r")>;
718 "CSNEG(W|X)r")>;
737 "CSNEG(W|X)r")>;
H A DAArch64SchedA64FX.td612 "CSNEG(W|X)r")>;
632 "CSNEG(W|X)r")>;
649 "CSNEG(W|X)r")>;
H A DAArch64SchedCyclone.td149 // CSEL,CSINC,CSINV,CSNEG
H A DAArch64SchedTSV110.td404 def : InstRW<[TSV110Wr_1cyc_1ALUAB], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedAmpere1.td952 (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
H A DAArch64SchedAmpere1B.td934 (instregex "(CSEL|CSINC|CSINV|CSNEG)(X|W)")>;
H A DAArch64SchedFalkorDetails.td894 def : InstRW<[FalkorWr_1XYZ_1cyc], (instregex "^(CSEL|CSINC|CSINV|CSNEG)(W|X)r$")>;
H A DAArch64SchedOryon.td701 "^CSNEG(W|X)r", "^CSINC(W|X)r")>;
H A DAArch64SchedKryoDetails.td549 (instregex "(CSINC|CSNEG)(W|X)r")>;
H A DAArch64ISelLowering.cpp11334 Opcode = AArch64ISD::CSNEG; in LowerSELECT_CC()
11394 } else if (Opcode == AArch64ISD::CSNEG && RHSVal && RHSVal->isOne()) { in LowerSELECT_CC()
18565 CSNeg = DAG.getNode(AArch64ISD::CSNEG, DL, VT, And, And, CCVal, Cmp); in BuildSREMPow2()
18576 CSNeg = DAG.getNode(AArch64ISD::CSNEG, DL, VT, AndPos, AndNeg, CCVal, in BuildSREMPow2()
20607 LHS.getOpcode() != AArch64ISD::CSNEG) { in performAddCSelIntoCSinc()
20610 LHS.getOpcode() != AArch64ISD::CSNEG) { in performAddCSelIntoCSinc()
20630 !(LHS.getOpcode() == AArch64ISD::CSNEG && in performAddCSelIntoCSinc()
20643 if (LHS.getOpcode() == AArch64ISD::CSNEG && CTVal->isOne() && in performAddCSelIntoCSinc()
20659 (LHS.getOpcode() == AArch64ISD::CSNEG && CFVal->isAllOnes())) && in performAddCSelIntoCSinc()
H A DAArch64InstrInfo.td826 def AArch64csneg : SDNode<"AArch64ISD::CSNEG", SDT_AArch64CSel>;
3360 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;