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Searched refs:CPol (Results 1 – 17 of 17) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIMemoryLegalizer.cpp287 AMDGPU::CPol::CPol Bit) const;
372 return enableNamedBit(MI, AMDGPU::CPol::GLC); in enableGLCBit()
378 return enableNamedBit(MI, AMDGPU::CPol::SLC); in enableSLCBit()
476 return enableNamedBit(MI, AMDGPU::CPol::SC0); in enableSC0Bit()
482 return enableNamedBit(MI, AMDGPU::CPol::SC1); in enableSC1Bit()
488 return enableNamedBit(MI, AMDGPU::CPol::NT); in enableNTBit()
525 return enableNamedBit(MI, AMDGPU::CPol::DLC); in enableDLCBit()
571 AMDGPU::CPol::CPol Value) const;
575 AMDGPU::CPol::CPol Value) const;
937 AMDGPU::CPol::CPol Bit) const { in enableNamedBit()
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H A DMIMGInstructions.td428 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
441 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
453 Dim:$dim, UNorm:$unorm, CPol:$cpol,
466 Dim:$dim, UNorm:$unorm, CPol:$cpol,
478 Dim:$dim, UNorm:$unorm, CPol:$cpol,
491 Dim:$dim, UNorm:$unorm, CPol:$cpol,
504 CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe),
518 CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe,
535 CPol:$cpol, R128A16:$r128, A16:$a16, TFE:$tfe,
685 DMask:$dmask, UNorm:$unorm, CPol:$cpol,
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H A DSILoadStoreOptimizer.cpp118 unsigned CPol = 0; member
850 CPol = LSO.TII->getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
1081 if (CI.CPol != Paired.CPol) in offsetsCanBeCombined()
1525 New.addImm(CI.CPol).addMemOperand(combineKnownAdjacentMMOs(CI, Paired)); in mergeSMemLoadImmPair()
1564 .addImm(CI.CPol) // cpol in mergeBufferLoadPair()
1609 .addImm(CI.CPol) // cpol in mergeTBufferLoadPair()
1652 .addImm(CI.CPol) // cpol in mergeTBufferStorePair()
1680 .addImm(CI.CPol) in mergeFlatLoadPair()
1710 .addImm(CI.CPol) in mergeFlatStorePair()
1971 .addImm(CI.CPol) // cpol in mergeBufferStorePair()
H A DSIDefines.h359 namespace CPol {
361 enum CPol { enum
H A DAMDGPUInstructionSelector.cpp2125 unsigned CPol = MI.getOperand(ArgOffset + Intr->CachePolicyIndex).getImm(); in selectImageIntrinsic() local
2127 CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization in selectImageIntrinsic()
2128 if (CPol & ~((IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12) | in selectImageIntrinsic()
2129 AMDGPU::CPol::VOLATILE)) in selectImageIntrinsic()
2243 MIB.addImm(CPol); in selectImageIntrinsic()
3467 MIB.addImm(Aux & (IsGFX12Plus ? AMDGPU::CPol::ALL in selectBufferLoadLds()
3468 : AMDGPU::CPol::ALL_pregfx12)); // cpol in selectBufferLoadLds()
3470 Aux & (IsGFX12Plus ? AMDGPU::CPol::SWZ : AMDGPU::CPol::SWZ_pregfx12) in selectBufferLoadLds()
6737 (AMDGPU::isGFX12Plus(STI) ? AMDGPU::CPol::ALL in renderExtractCPol()
6738 : AMDGPU::CPol::ALL_pregfx12)); in renderExtractCPol()
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H A DSIInstrInfo.td993 ? AMDGPU::CPol::ALL
994 : AMDGPU::CPol::ALL_pregfx12),
1001 ? AMDGPU::CPol::SWZ
1002 : AMDGPU::CPol::SWZ_pregfx12);
1008 ? AMDGPU::CPol::ALL
1009 : AMDGPU::CPol::ALL_pregfx12);
1010 return CurDAG->getTargetConstant(cpol | AMDGPU::CPol::GLC, SDLoc(N), MVT::i8);
1215 def CPol : CustomOperand<i32, 1>;
1216 def CPol_0 : DefaultOperand<CPol, 0>;
1217 def CPol_GLC1 : DefaultOperand<CPol, 1>;
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H A DSMInstructions.td128 !con((ins baseClass:$sbase), offsets.Ins, (ins CPol:$cpol)),
143 offsets.Ins, (ins CPol:$cpol)),
506 let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, CPol:$cpol);
788 let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, CPol:$cpol);
1486 let InOperandList = !con((ins BaseClass:$sbase), offsets.Ins, (ins CPol:$cpol));
H A DFLATInstructions.td225 !if(HasTiedOutput, (ins CPol:$cpol, vdata_op:$vdst_in),
377 (ins flat_offset:$offset, CPol:$cpol)),
413 FLAT_Pseudo<opName, (outs), (ins CPol:$cpol), "$cpol", [(node)]> {
461 !if(HasTiedOutput, (ins CPol:$cpol, getLdStRegisterOperand<regClass>.ret:$vdst_in),
586 (ins VGPR_32:$vaddr, SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol:$cpol),
588 (ins SReg_32_XEXEC_HI:$saddr, flat_offset:$offset, CPol:$cpol),
590 (ins VGPR_32:$vaddr, flat_offset:$offset, CPol:$cpol),
591 (ins flat_offset:$offset, CPol:$cpol)))),
H A DAMDGPULowerBufferFatPointers.cpp1696 Aux |= AMDGPU::CPol::VOLATILE; in handleMemoryInst()
1847 Aux |= AMDGPU::CPol::SLC; in visitAtomicCmpXchgInst()
1849 Aux |= AMDGPU::CPol::VOLATILE; in visitAtomicCmpXchgInst()
H A DSIISelLowering.cpp1283 if (Aux->getZExtValue() & AMDGPU::CPol::VOLATILE) in getTgtMemIntrinsic()
8729 unsigned CPol = Op.getConstantOperandVal(ArgOffset + Intr->CachePolicyIndex); in lowerImage() local
8731 CPol |= AMDGPU::CPol::GLC; // TODO no-return optimization in lowerImage()
8732 if (CPol & ~((IsGFX12Plus ? AMDGPU::CPol::ALL : AMDGPU::CPol::ALL_pregfx12) | in lowerImage()
8733 AMDGPU::CPol::VOLATILE)) in lowerImage()
8762 Ops.push_back(DAG.getTargetConstant(CPol, DL, MVT::i32)); in lowerImage()
9133 unsigned CPol = Op.getConstantOperandVal(3); in LowerINTRINSIC_WO_CHAIN() local
9136 if (CPol & ~((Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12) in LowerINTRINSIC_WO_CHAIN()
9137 ? AMDGPU::CPol::ALL in LowerINTRINSIC_WO_CHAIN()
9138 : AMDGPU::CPol::ALL_pregfx12)) in LowerINTRINSIC_WO_CHAIN()
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H A DBUFInstructions.td664 … (ins SReg_128_XNULL:$srsrc, SCSrc_b32:$soffset, Offset:$offset, CPol:$cpol, i1imm:$swz),
688 dag CPol = !if(vdata_in, (ins CPol_GLC_WithDefault:$cpol),
691 dag ret = !con(Data, MainInputs, CPol);
H A DSIRegisterInfo.cpp1919 MIB.addImm(LastUse ? AMDGPU::CPol::TH_LU : 0); // cpol in buildSpillLoadStore()
H A DSIInstrInfo.cpp7201 if (const MachineOperand *CPol = in legalizeOperands() local
7203 MIB.addImm(CPol->getImm()); in legalizeOperands()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp157 const int64_t TH = Imm & CPol::TH; in printCPol()
158 const int64_t Scope = Imm & CPol::SCOPE; in printCPol()
166 if (Imm & CPol::GLC) in printCPol()
170 if (Imm & CPol::SLC) in printCPol()
172 if ((Imm & CPol::DLC) && AMDGPU::isGFX10Plus(STI)) in printCPol()
174 if ((Imm & CPol::SCC) && AMDGPU::isGFX90A(STI)) in printCPol()
176 if (Imm & ~CPol::ALL_pregfx12) in printCPol()
189 bool IsStore = (THType == AMDGPU::CPol::TH_TYPE_STORE); in printTH()
193 if (THType == AMDGPU::CPol::TH_TYPE_ATOMIC) { in printTH()
195 if (TH & AMDGPU::CPol::TH_ATOMIC_CASCADE) { in printTH()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp1849 const unsigned CPol);
5281 unsigned CPol = Inst.getOperand(CPolPos).getImm(); in validateCoherencyBits() local
5284 return validateTHAndScopeBits(Inst, Operands, CPol); in validateCoherencyBits()
5288 if (CPol && (isSI() || isCI())) { in validateCoherencyBits()
5293 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) { in validateCoherencyBits()
5299 if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) { in validateCoherencyBits()
5317 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { in validateCoherencyBits()
5323 if (CPol & CPol::GLC) { in validateCoherencyBits()
5339 const unsigned CPol) { in validateTHAndScopeBits() argument
5340 const unsigned TH = CPol & AMDGPU::CPol::TH; in validateTHAndScopeBits()
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/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp806 unsigned CPol = in getInstruction() local
808 AMDGPU::CPol::GLC : 0; in getInstruction()
810 insertNamedMCOperand(MI, MCOperand::createImm(CPol), in getInstruction()
812 } else if (CPol) { in getInstruction()
813 MI.getOperand(CPolPos).setImm(MI.getOperand(CPolPos).getImm() | CPol); in getInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp716 return CPol::TH_TYPE_ATOMIC; in getTemporalHintType()
721 return CPol::TH_TYPE_STORE; in getTemporalHintType()
726 return CPol::TH_TYPE_LOAD; in getTemporalHintType()