Lines Matching refs:CPol
1768 const unsigned CPol);
4911 unsigned CPol = Inst.getOperand(CPolPos).getImm(); in validateCoherencyBits() local
4914 return validateTHAndScopeBits(Inst, Operands, CPol); in validateCoherencyBits()
4918 if (CPol && (isSI() || isCI())) { in validateCoherencyBits()
4923 if (CPol & ~(AMDGPU::CPol::GLC | AMDGPU::CPol::DLC)) { in validateCoherencyBits()
4929 if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) { in validateCoherencyBits()
4947 if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) { in validateCoherencyBits()
4953 if (CPol & CPol::GLC) { in validateCoherencyBits()
4969 const unsigned CPol) { in validateTHAndScopeBits() argument
4970 const unsigned TH = CPol & AMDGPU::CPol::TH; in validateTHAndScopeBits()
4971 const unsigned Scope = CPol & AMDGPU::CPol::SCOPE; in validateTHAndScopeBits()
4984 (!(TH & AMDGPU::CPol::TH_ATOMIC_RETURN))) in validateTHAndScopeBits()
4991 ((TH == AMDGPU::CPol::TH_NT_RT) || (TH == AMDGPU::CPol::TH_RT_NT) || in validateTHAndScopeBits()
4992 (TH == AMDGPU::CPol::TH_NT_HT))) in validateTHAndScopeBits()
4995 if (TH == AMDGPU::CPol::TH_BYPASS) { in validateTHAndScopeBits()
4996 if ((Scope != AMDGPU::CPol::SCOPE_SYS && in validateTHAndScopeBits()
4997 CPol & AMDGPU::CPol::TH_REAL_BYPASS) || in validateTHAndScopeBits()
4998 (Scope == AMDGPU::CPol::SCOPE_SYS && in validateTHAndScopeBits()
4999 !(CPol & AMDGPU::CPol::TH_REAL_BYPASS))) in validateTHAndScopeBits()
5008 if (!(CPol & AMDGPU::CPol::TH_TYPE_ATOMIC)) in validateTHAndScopeBits()
5011 if (!(CPol & AMDGPU::CPol::TH_TYPE_STORE)) in validateTHAndScopeBits()
5014 if (!(CPol & AMDGPU::CPol::TH_TYPE_LOAD)) in validateTHAndScopeBits()
6515 .Case("nt", AMDGPU::CPol::NT) in getCPolKind()
6516 .Case("sc0", AMDGPU::CPol::SC0) in getCPolKind()
6517 .Case("sc1", AMDGPU::CPol::SC1) in getCPolKind()
6522 .Case("dlc", AMDGPU::CPol::DLC) in getCPolKind()
6523 .Case("glc", AMDGPU::CPol::GLC) in getCPolKind()
6524 .Case("scc", AMDGPU::CPol::SCC) in getCPolKind()
6525 .Case("slc", AMDGPU::CPol::SLC) in getCPolKind()
6577 unsigned CPol = getCPolKind(getId(), Mnemo, Disabling); in parseCPol() local
6578 if (!CPol) in parseCPol()
6583 if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC) in parseCPol()
6586 if (!isGFX90A() && CPol == AMDGPU::CPol::SCC) in parseCPol()
6589 if (Seen & CPol) in parseCPol()
6593 Enabled |= CPol; in parseCPol()
6595 Seen |= CPol; in parseCPol()
6608 Scope = AMDGPU::CPol::SCOPE_CU; // default; in parseScope()
6619 .Case("SCOPE_CU", AMDGPU::CPol::SCOPE_CU) in parseScope()
6620 .Case("SCOPE_SE", AMDGPU::CPol::SCOPE_SE) in parseScope()
6621 .Case("SCOPE_DEV", AMDGPU::CPol::SCOPE_DEV) in parseScope()
6622 .Case("SCOPE_SYS", AMDGPU::CPol::SCOPE_SYS) in parseScope()
6632 TH = AMDGPU::CPol::TH_RT; // default in parseTH()
6641 TH = AMDGPU::CPol::TH_RT; in parseTH()
6646 TH = AMDGPU::CPol::TH_TYPE_ATOMIC; in parseTH()
6648 TH = AMDGPU::CPol::TH_TYPE_LOAD; in parseTH()
6650 TH = AMDGPU::CPol::TH_TYPE_STORE; in parseTH()
6656 TH |= AMDGPU::CPol::TH_REAL_BYPASS; in parseTH()
6659 if (TH & AMDGPU::CPol::TH_TYPE_ATOMIC) in parseTH()
6661 .Case("RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN) in parseTH()
6662 .Case("RT", AMDGPU::CPol::TH_RT) in parseTH()
6663 .Case("RT_RETURN", AMDGPU::CPol::TH_ATOMIC_RETURN) in parseTH()
6664 .Case("NT", AMDGPU::CPol::TH_ATOMIC_NT) in parseTH()
6665 .Case("NT_RETURN", AMDGPU::CPol::TH_ATOMIC_NT | in parseTH()
6666 AMDGPU::CPol::TH_ATOMIC_RETURN) in parseTH()
6667 .Case("CASCADE_RT", AMDGPU::CPol::TH_ATOMIC_CASCADE) in parseTH()
6668 .Case("CASCADE_NT", AMDGPU::CPol::TH_ATOMIC_CASCADE | in parseTH()
6669 AMDGPU::CPol::TH_ATOMIC_NT) in parseTH()
6673 .Case("RT", AMDGPU::CPol::TH_RT) in parseTH()
6674 .Case("NT", AMDGPU::CPol::TH_NT) in parseTH()
6675 .Case("HT", AMDGPU::CPol::TH_HT) in parseTH()
6676 .Case("LU", AMDGPU::CPol::TH_LU) in parseTH()
6677 .Case("RT_WB", AMDGPU::CPol::TH_RT_WB) in parseTH()
6678 .Case("NT_RT", AMDGPU::CPol::TH_NT_RT) in parseTH()
6679 .Case("RT_NT", AMDGPU::CPol::TH_RT_NT) in parseTH()
6680 .Case("NT_HT", AMDGPU::CPol::TH_NT_HT) in parseTH()
6681 .Case("NT_WB", AMDGPU::CPol::TH_NT_WB) in parseTH()
6682 .Case("BYPASS", AMDGPU::CPol::TH_BYPASS) in parseTH()