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Searched refs:CPSR (Results 1 – 25 of 34) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h122 MIB.addReg(ARM::CPSR, RegState::Define);
130 MIB.addReg(ARM::CPSR);
158 MIB.addReg(ARM::CPSR);
186 MIB.addReg(ARM::CPSR);
H A DThumb2SizeReduction.cpp256 return is_contained(MCID.implicit_defs(), ARM::CPSR); in HasImplicitCPSRDef()
302 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
382 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
655 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
816 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
880 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
907 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
959 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) in ReduceToNarrow()
984 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
999 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
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H A DARMInstrThumb.td415 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR.
419 let Defs = [CPSR];
968 let isCommutable = 1, Uses = [CPSR] in
1002 /// instruction modifies the CPSR register.
1005 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
1006 let hasPostISelHook = 1, Defs = [CPSR] in {
1007 let isCommutable = 1, Uses = [CPSR] in
1010 [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
1011 CPSR))]>,
1017 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
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H A DThumb1InstrInfo.cpp69 if (UsedRegs.available(ARM::CPSR)) { in copyPhysReg()
72 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
H A DARMFeatures.td387 /// Some instructions update CPSR partially, which can add false dependency for
389 /// mapped to a separate physical register. Avoid partial CPSR update for these
392 /// that partially update CPSR and add false dependency on the previous
393 /// CPSR setting instruction.
396 "Avoid CPSR partial update for OOO execution">;
398 /// Disable +1 predication cost for instructions updating CPSR.
400 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
404 "Disable +1 predication cost for instructions updating CPSR">;
H A DARMFastISel.cpp233 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
245 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { in DefinesOptionalPredicate() argument
252 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
253 *CPSR = true; in DefinesOptionalPredicate()
290 bool CPSR = false; in AddOptionalDefs() local
291 if (DefinesOptionalPredicate(MI, &CPSR)) in AddOptionalDefs()
292 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); in AddOptionalDefs()
1254 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1277 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1315 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
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H A DARMBaseInstrInfo.cpp626 MI.getOperand(1).getReg() != ARM::CPSR) && in PredicateInstruction()
667 bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR); in ClobbersPredicate()
668 bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR; in ClobbersPredicate()
688 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
766 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
845 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
865 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
985 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
988 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
2267 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
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H A DARMInstrInfo.td85 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
1694 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1695 let hasPostISelHook = 1, Defs = [CPSR] in {
1701 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1706 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1713 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1720 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1728 let hasPostISelHook = 1, Defs = [CPSR] in {
1733 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
1739 [(set GPR:$Rd, CPSR, (opnode so_reg_imm:$shift,
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H A DARMInstrThumb2.td726 /// changed to modify CPSR.
865 /// instruction modifies the CPSR register.
868 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
869 let hasPostISelHook = 1, Defs = [CPSR] in {
877 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
883 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
892 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
900 let hasPostISelHook = 1, Defs = [CPSR] in {
906 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
913 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
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H A DThumb2ITBlockPass.cpp172 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
H A DARMInstructionSelector.cpp604 .add(predOps(Cond, ARM::CPSR)); in insertComparison()
798 .add(predOps(ARMCC::EQ, ARM::CPSR)); in selectSelect()
1147 .add(predOps(ARMCC::NE, ARM::CPSR)); in select()
H A DARMExpandPseudoInsts.cpp1189 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1313 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1871 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1895 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1988 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
1994 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2016 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2356 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2558 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2770 .addReg(ARM::CPSR, RegState::Undef) in ExpandMI()
H A DARMAsmPrinter.cpp1865 .addReg(ARM::CPSR) in emitInstruction()
1921 .addReg(ARM::CPSR) in emitInstruction()
2052 .addReg(ARM::CPSR) in emitInstruction()
2071 .addReg(ARM::CPSR) in emitInstruction()
2086 .addReg(ARM::CPSR) in emitInstruction()
H A DMVETPAndVPTOptimisationsPass.cpp200 MIB.addReg(ARM::CPSR, RegState::Define); in RevertWhileLoopSetup()
209 MIB.addReg(ARM::CPSR); in RevertWhileLoopSetup()
H A DARMLowOverheadLoops.cpp1441 RDA->isSafeToDefRegAt(MI, MCRegister::from(ARM::CPSR), Ignore); in RevertLoopDec()
1471 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
1482 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
H A DARMISelLowering.cpp4847 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, ARM::CPSR, in getARMCmp()
5004 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSignedALUO()
5149 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT()
5548 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5583 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerSELECT_CC()
5690 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in OptimizeVFPBrcond()
5739 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBRCOND()
5793 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
5802 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
5819 SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); in LowerBR_CC()
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H A DThumb1FrameLowering.cpp462 .addDef(ARM::CPSR) in emitPrologue()
468 .addDef(ARM::CPSR) in emitPrologue()
H A DARMRegisterInfo.td184 def CPSR : ARMReg<0, "cpsr">;
404 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
H A DThumb2InstrInfo.cpp575 !MI.definesRegister(ARM::CPSR, /*TRI=*/nullptr)) { in rewriteT2FrameIndex()
H A DARMBaseInstrInfo.h578 return MachineOperand::CreateReg(ARM::CPSR,
H A DARMLoadStoreOptimizer.cpp211 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead()) in definesCPSR()
640 (MBB.computeRegisterLiveness(TRI, ARM::CPSR, InsertBefore, 20) == in CreateLoadStoreMulti()
3181 if (Increment->definesRegister(ARM::CPSR, /*TRI=*/nullptr) || in DistributeIncrements()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp179 if (MO.isReg() && MO.getReg() == ARM::CPSR && in isCPSRDefined()
245 {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, in initLLVMToCVRegMapping()
H A DARMMCCodeEmitter.cpp311 // The operand is either reg0 or CPSR. The 's' bit is encoded as '0' or in getCCOutOpValue()
313 return MI.getOperand(Op).getReg() == ARM::CPSR; in getCCOutOpValue()
714 (MCOp2.getReg() == 0 || MCOp2.getReg() == ARM::CPSR)) { in getThumbCBTargetOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td70 def CPSR : SparcCtrlReg<0, "csr">; // Co-processor state register.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2535 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
7169 ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, Loc, *this)); in ParseInstruction()
10374 Inst.getOperand(5).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10424 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10431 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0)); in processInstruction()
10477 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10485 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0)); in processInstruction()
10686 Inst.getOperand(5).getReg() != (inITBlock() ? 0 : ARM::CPSR) || in processInstruction()
10856 Inst.getOperand(4).getReg() == (inITBlock() ? 0 : ARM::CPSR) && in processInstruction()
10877 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
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