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Searched refs:CPSR (Results 1 – 25 of 37) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVETailPredUtils.h122 MIB.addReg(ARM::CPSR, RegState::Define);
130 MIB.addReg(ARM::CPSR);
158 MIB.addReg(ARM::CPSR);
186 MIB.addReg(ARM::CPSR);
H A DThumb2SizeReduction.cpp253 return is_contained(MCID.implicit_defs(), ARM::CPSR); in HasImplicitCPSRDef()
299 if (Reg == 0 || Reg == ARM::CPSR) in canAddPseudoFlagDep()
379 if (Reg == 0 || Reg == ARM::CPSR) in VerifyLowRegs()
652 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
816 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceTo2Addr()
880 if (!Reg || Reg == ARM::CPSR) in ReduceToNarrow()
907 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); in ReduceToNarrow()
959 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) in ReduceToNarrow()
984 if (MO.getReg() != ARM::CPSR) in UpdateCPSRDef()
999 if (MO.getReg() != ARM::CPSR) in UpdateCPSRUse()
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H A DARMInstrThumb.td414 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR.
418 let Defs = [CPSR];
967 let isCommutable = 1, Uses = [CPSR] in
1001 /// instruction modifies the CPSR register.
1004 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
1005 let hasPostISelHook = 1, Defs = [CPSR] in {
1006 let isCommutable = 1, Uses = [CPSR] in
1009 [(set tGPR:$Rdn, CPSR, (ARMadde tGPR:$Rn, tGPR:$Rm,
1010 CPSR))]>,
1016 [(set tGPR:$Rd, CPSR, (ARMaddc tGPR:$Rm,
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H A DARMInstrThumb2.td726 /// changed to modify CPSR.
865 /// instruction modifies the CPSR register.
868 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand.
869 let hasPostISelHook = 1, Defs = [CPSR] in {
877 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
883 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
892 [(set rGPR:$Rd, CPSR, (opnode GPRnopc:$Rn,
900 let hasPostISelHook = 1, Defs = [CPSR] in {
906 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm,
913 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm,
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H A DARMInstrInfo.td20 /// Value type used for "flags" operands / results (either CPSR or FPSCR_NZCV).
114 // SDTBinaryArithWithFlagsInOut - RES1, CPSR = op LHS, RHS, CPSR
1713 /// AdjustInstrPostInstrSelection after giving them an optional CPSR operand.
1714 let hasPostISelHook = 1, Defs = [CPSR] in {
1720 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
1725 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, GPR:$Rm))]>,
1732 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1739 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn,
1747 let hasPostISelHook = 1, Defs = [CPSR] in {
1752 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
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H A DThumb1InstrInfo.cpp70 if (UsedRegs.available(ARM::CPSR)) { in copyPhysReg()
73 ->addRegisterDead(ARM::CPSR, RegInfo); in copyPhysReg()
H A DARMLatencyMutations.cpp488 return MI->getDesc().hasImplicitUseOfPhysReg(ARM::CPSR); in hasImplicitCPSRUse()
540 (Dep.isAssignedRegDep() && Dep.getReg() == ARM::CPSR) ? 0 : 1); in makeBundleAssumptions()
544 Dep.isAssignedRegDep() && Dep.getReg() != ARM::CPSR) { in makeBundleAssumptions()
684 if (Dep.isAssignedRegDep() && Dep.getReg() == ARM::CPSR && in modifyBypasses()
908 if (Dep.isAssignedRegDep() && Dep.getReg() == ARM::CPSR && in modifyBypasses()
H A DARMBaseInstrInfo.cpp451 MI.getOperand(1).getReg() != ARM::CPSR) && in PredicateInstruction()
492 bool ClobbersCPSR = MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR); in ClobbersPredicate()
493 bool IsCPSR = MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR; in ClobbersPredicate()
513 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead()) in isCPSRDefined()
591 if (MO.getReg() != ARM::CPSR) in IsCPSRDead()
670 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc)); in copyFromCPSR()
690 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define); in copyToCPSR()
812 } else if (SrcReg == ARM::CPSR) { in copyPhysReg()
815 } else if (DestReg == ARM::CPSR) { in copyPhysReg()
2110 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstructionImpl()
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H A DARMFeatures.td390 /// Some instructions update CPSR partially, which can add false dependency for
392 /// mapped to a separate physical register. Avoid partial CPSR update for these
395 /// that partially update CPSR and add false dependency on the previous
396 /// CPSR setting instruction.
399 "Avoid CPSR partial update for OOO execution">;
408 /// Disable +1 predication cost for instructions updating CPSR.
410 /// True if disable +1 predication cost for instructions updating CPSR. Enabled for Cortex-A57.
414 "Disable +1 predication cost for instructions updating CPSR">;
H A DARMFastISel.cpp258 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
270 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { in DefinesOptionalPredicate() argument
277 if (MO.getReg() == ARM::CPSR) in DefinesOptionalPredicate()
278 *CPSR = true; in DefinesOptionalPredicate()
315 bool CPSR = false; in AddOptionalDefs() local
316 if (DefinesOptionalPredicate(MI, &CPSR)) in AddOptionalDefs()
317 MIB.add(CPSR ? t1CondCodeOp() : condCodeOp()); in AddOptionalDefs()
1296 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); in SelectBranch()
1319 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
1358 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); in SelectBranch()
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H A DThumbRegisterInfo.cpp184 auto isCpsr = [](auto &MO) { return MO.getReg() == ARM::CPSR; }; in emitThumbRegPlusImmInReg()
199 auto liveOutIsCpsr = [](auto &Out) { return Out.PhysReg == ARM::CPSR; }; in emitThumbRegPlusImmInReg()
212 .addReg(ARM::CPSR, RegState::Implicit); in emitThumbRegPlusImmInReg()
H A DThumb2ITBlockPass.cpp168 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
H A DARMExpandPseudoInsts.cpp1188 CLRM.addReg(ARM::CPSR, RegState::Define | RegState::Implicit); in CMSEClearGPRegs()
1312 .addReg(ARM::CPSR, RegState::Kill); in CMSEClearFPRegsV8()
1908 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
1932 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP()
2028 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2034 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2056 .addReg(ARM::CPSR, RegState::Kill); in ExpandCMP_SWAP_64()
2398 .addReg(ARM::CPSR, RegState::Define) in ExpandMI()
2600 .addReg(ARM::CPSR, RegState::Define); in ExpandMI()
2812 .addReg(ARM::CPSR, RegState::Undef) in ExpandMI()
H A DARMInstructionSelector.cpp604 .add(predOps(Cond, ARM::CPSR)); in insertComparison()
798 .add(predOps(ARMCC::EQ, ARM::CPSR)); in selectSelect()
1167 .add(predOps(ARMCC::NE, ARM::CPSR)); in select()
H A DARMAsmPrinter.cpp1899 .addReg(ARM::CPSR) in emitInstruction()
1955 .addReg(ARM::CPSR) in emitInstruction()
2086 .addReg(ARM::CPSR) in emitInstruction()
2105 .addReg(ARM::CPSR) in emitInstruction()
2120 .addReg(ARM::CPSR) in emitInstruction()
H A DARMInstrVFP.td561 Uses = [CPSR], AddedComplexity = 4, isUnpredicable = 1 in {
566 (ARMcmov (f16 HPR:$Sm), (f16 HPR:$Sn), CC, CPSR))]>,
572 [(set SPR:$Sd, (ARMcmov SPR:$Sm, SPR:$Sn, CC, CPSR))]>,
579 (ARMcmov (f64 DPR:$Dm), (f64 DPR:$Dn), CC, CPSR))]>,
2483 def : Pat<(ARMcmov f64:$Dn, f64:$Dm, imm:$cc, CPSR),
2484 (VMOVDcc $Dn, $Dm, imm:$cc, CPSR)>,
2487 def : Pat<(ARMcmov f32:$Sn, f32:$Sm, imm:$cc, CPSR),
2488 (VMOVScc $Sn, $Sm, imm:$cc, CPSR)>,
2491 def : Pat<(ARMcmov f16:$Sn, f16:$Sm, imm:$cc, CPSR),
2492 (VMOVHcc $Sn, $Sm, imm:$cc, CPSR)>,
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H A DARMLowOverheadLoops.cpp1435 RDA->isSafeToDefRegAt(MI, MCRegister::from(ARM::CPSR), Ignore); in RevertLoopDec()
1465 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
1476 MIB.addReg(ARM::CPSR); in RevertLoopEndDec()
H A DMVETPAndVPTOptimisationsPass.cpp199 MIB.addReg(ARM::CPSR, RegState::Define); in RevertWhileLoopSetup()
208 MIB.addReg(ARM::CPSR); in RevertWhileLoopSetup()
H A DThumb1FrameLowering.cpp434 .addDef(ARM::CPSR) in emitPrologue()
440 .addDef(ARM::CPSR) in emitPrologue()
H A DARMRegisterInfo.td184 def CPSR : ARMReg<0, "cpsr">;
404 def CCR : RegisterClass<"ARM", [i32], 32, (add CPSR)> {
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcRegisterInfo.td70 def CPSR : SparcCtrlReg<0, "csr">; // Co-processor state register.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.cpp180 if (MO.isReg() && MO.getReg() == ARM::CPSR && in isCPSRDefined()
246 {codeview::RegisterId::ARM_CPSR, ARM::CPSR}, in initLLVMToCVRegMapping()
H A DARMMCCodeEmitter.cpp311 return MI.getOperand(Op).getReg() == ARM::CPSR; in getCCOutOpValue()
721 (!MCOp2.getReg() || MCOp2.getReg() == ARM::CPSR)) { in HasConditionalBranch()
/freebsd/sys/contrib/edk2/Include/Protocol/
H A DDebugSupport.h507 UINT32 CPSR; member
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/AsmParser/
H A DARMAsmParser.cpp2536 unsigned RegNum = getCondCode() == ARMCC::AL ? ARM::NoRegister : ARM::CPSR; in addCondCodeOperands()
7201 CarrySetting ? ARM::CPSR : ARM::NoRegister, Loc, *this)); in parseInstruction()
10449 (inITBlock() ? ARM::NoRegister : ARM::CPSR) && in processInstruction()
10499 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : ARM::NoRegister)); in processInstruction()
10506 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : ARM::NoRegister)); in processInstruction()
10552 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : ARM::NoRegister)); in processInstruction()
10560 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : ARM::NoRegister)); in processInstruction()
10764 (inITBlock() ? ARM::NoRegister : ARM::CPSR)) in processInstruction()
10943 (inITBlock() ? ARM::NoRegister : ARM::CPSR) && in processInstruction()
10964 Inst.getOperand(4).getReg() == ARM::CPSR && in processInstruction()
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