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Searched refs:CMOV (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FlagsCopyLowering.cpp876 case X86::CMOV##A##_Fp32: \ in getImplicitCondFromMI()
877 case X86::CMOV##A##_Fp64: \ in getImplicitCondFromMI()
878 case X86::CMOV##A##_Fp80: \ in getImplicitCondFromMI()
H A DX86InstrCMovSetCC.td15 // CMOV instructions.
H A DX86ISelLowering.h134 CMOV, enumerator
H A DX86InstrFragments.td154 def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>;
H A DX86ISelLowering.cpp25178 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, T1.getValueType(), T2, T1, in LowerSELECT()
25196 SDValue Cmov = DAG.getNode(X86ISD::CMOV, DL, MVT::i32, Ops); in LowerSELECT()
25203 return DAG.getNode(X86ISD::CMOV, DL, Op.getValueType(), Ops, Op->getFlags()); in LowerSELECT()
28098 SDValue isValid = DAG.getNode(X86ISD::CMOV, dl, Op->getValueType(1), Ops); in LowerINTRINSIC_W_CHAIN()
29097 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops); in LowerCTLZ()
29137 return DAG.getNode(X86ISD::CMOV, dl, VT, Ops); in LowerCTTZ()
29240 return DAG.getNode(X86ISD::CMOV, DL, VT, Ops); in LowerABS()
29494 return DAG.getNode(X86ISD::CMOV, dl, VT, Diff1, Diff0, in LowerABD()
29509 SDValue AbsDiff = DAG.getNode(X86ISD::CMOV, dl, WideVT, Diff1, Diff0, in LowerABD()
34966 NODE_NAME_CASE(CMOV) in getTargetNodeName()
[all …]
H A DX86InstrCompiler.td565 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
568 def CMOV#NAME : I<0, Pseudo,
H A DX86InstrAsmAlias.td795 // CMOV SETCC SETZUCC Aliases
/freebsd/sys/contrib/xen/arch-x86/
H A Dcpufeatureset.h109 XEN_CPUFEATURE(CMOV, 0*32+15) /*A CMOV instruction (FCMOVCC and FCOMI too if FPU present)…
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kInstrCompiler.td53 // CMOV* - Used to implement the SELECT DAG operation. Expanded after
H A DM68kInstrInfo.td151 def MxCmov : SDNode<"M68kISD::CMOV", MxSDT_Cmov>;
H A DM68kISelLowering.cpp2406 DAG.getNode(M68kISD::CMOV, DL, T1.getValueType(), T2, T1, CC, Cond); in LowerSELECT()
2425 return DAG.getNode(M68kISD::CMOV, DL, Op.getValueType(), Ops); in LowerSELECT()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h31 CMOV, // Select between two values using the result of comparison. enumerator
H A DVEInstrInfo.td460 def cmov : SDNode<"VEISD::CMOV", SDT_Cmov>;
723 // Multiclass for CMOV instructions.
1313 // Section 8.5.11 - CMOV (Conditional Move)
2029 // CMOV %res, (63)0, %tmp ; set 1 if %tmp is true
2053 // Generic CMOV pattern matches
2054 // CMOV accepts i64 $t, $f, and result. So, we extend it to support
2057 // CMOV for i32
2077 // CMOV for f32
2098 // CMOV for f64
2111 // CMOV for f128
H A DVEISelLowering.cpp928 TARGET_NODE_CASE(CMOV) in getTargetNodeName()
2809 return DAG.getNode(VEISD::CMOV, DL, VT, Ops); in combineSelect()
2877 return DAG.getNode(VEISD::CMOV, DL, VT, Ops); in combineSelectCC()
2916 case VEISD::CMOV: in isI32Insn()
2959 User->getOpcode() == ISD::SELECT || User->getOpcode() == VEISD::CMOV) in isI32InsnAllUses()
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DX86TargetParser.def142 X86_FEATURE_COMPAT(CMOV, "cmov", 0)
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSiFiveP500.td59 // CMOV
H A DRISCVSchedSiFiveP800.td129 // CMOV
H A DRISCVSchedSiFiveP400.td192 // CMOV
H A DRISCVSchedSiFiveP600.td369 // CMOV
H A DRISCVISelLowering.cpp9110 SDValue CMOV = in lowerSELECT() local
9112 SDValue NOT = DAG.getNOT(DL, CMOV, VT); in lowerSELECT()
9128 SDValue CMOV = in lowerSELECT() local
9130 SDValue NOT = DAG.getNOT(DL, CMOV, VT); in lowerSELECT()
9183 SDValue CMOV = in lowerSELECT() local
9186 return DAG.getNode(ISD::ADD, DL, VT, CMOV, RHSVal); in lowerSELECT()
9199 SDValue CMOV = in lowerSELECT() local
9202 return DAG.getNode(ISD::XOR, DL, VT, CMOV, ConstVal); in lowerSELECT()
9208 SDValue CMOV = in lowerSELECT() local
9211 return DAG.getNode(ISD::ADD, DL, VT, CMOV, ConstVal); in lowerSELECT()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp1722 MAKE_CASE(ARMISD::CMOV) in getTargetNodeName()
5075 DAG.getNode(ARMISD::CMOV, dl, VT, TVal, FVal, ARMcc, OverflowCmp); in LowerSignedALUO()
5222 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) { in LowerSELECT()
5322 SDValue Low = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseLow, TrueLow, in getCMOV()
5324 SDValue High = DAG.getNode(ARMISD::CMOV, dl, MVT::i32, FalseHigh, TrueHigh, in getCMOV()
5329 return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, Flags); in getCMOV()
6414 DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, LoBigShift, ARMcc, CmpLo); in LowerShiftRightParts()
6424 DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift, ARMcc, CmpHi); in LowerShiftRightParts()
6456 DAG.getNode(ARMISD::CMOV, dl, VT, HiSmallShift, HiBigShift, ARMcc, CmpHi); in LowerShiftLeftParts()
6461 SDValue Lo = DAG.getNode(ARMISD::CMOV, dl, VT, LoSmallShift, in LowerShiftLeftParts()
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H A DARMISelLowering.h98 CMOV, // ARM conditional move instructions. enumerator
H A DARMISelDAGToDAG.cpp4222 case ARMISD::CMOV: { in Select()
4245 CurDAG->MorphNodeTo(N, ARMISD::CMOV, N->getVTList(), Ops); in Select()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp196 return DAG.getNode(ARCISD::CMOV, dl, TVal.getValueType(), TVal, FVal, in LowerSELECT_CC()
H A DARCInstrInfo.td55 def ARCcmov : SDNode<"ARCISD::CMOV", SDT_ARCcmov, [SDNPInGlue]>;

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