xref: /freebsd/sys/dev/bhnd/cores/chipc/chipcreg.h (revision 95ee2897e98f5d444f26ed2334cc7c439f9c16c6)
1 /*-
2  * SPDX-License-Identifier: ISC
3  *
4  * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5  * Copyright (c) 2010-2015 Broadcom Corporation
6  * All rights reserved.
7  *
8  * This file is derived from the sbchipc.h header contributed by Broadcom
9  * to to the Linux staging repository, as well as later revisions of sbchipc.h
10  * distributed with the Asus RT-N16 firmware source code release.
11  *
12  * Permission to use, copy, modify, and/or distribute this software for any
13  * purpose with or without fee is hereby granted, provided that the above
14  * copyright notice and this permission notice appear in all copies.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
18  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
21  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
22  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23  */
24 
25 #ifndef _BHND_CORES_CHIPC_CHIPCREG_H_
26 #define	_BHND_CORES_CHIPC_CHIPCREG_H_
27 
28 /** Evaluates to true if the given ChipCommon core revision supports
29  *  the CHIPC_CORECTRL register */
30 #define	CHIPC_HWREV_HAS_CORECTRL(hwrev)	((hwrev) >= 1)
31 
32 /** Evaluates to true if the given ChipCommon core revision provides
33  *  the core count via the chip identification register. */
34 #define	CHIPC_NCORES_MIN_HWREV(hwrev)	((hwrev) == 4 || (hwrev) >= 6)
35 
36 /** Evaluates to true if the given ChipCommon core revision supports
37  *  the CHIPC_CAPABILITIES_EXT register */
38 #define	CHIPC_HWREV_HAS_CAP_EXT(hwrev)	((hwrev) >= 35)
39 
40 /** Evaluates to true if the chipcommon core (determined from the provided
41  * @p _chipid (CHIPC_ID) register value) provides a pointer to the enumeration
42  * table via CHIPC_EROMPTR */
43 #define	CHIPC_HAS_EROMPTR(_chipid)	\
44 	(CHIPC_GET_BITS((_chipid), CHIPC_ID_BUS) != BHND_CHIPTYPE_SIBA)
45 
46 #define CHIPC_GET_FLAG(_value, _flag)	(((_value) & _flag) != 0)
47 #define	CHIPC_GET_BITS(_value, _field)	\
48 	((_value & _field ## _MASK) >> _field ## _SHIFT)
49 
50 #define	CHIPC_ID			0x00
51 #define	CHIPC_CAPABILITIES		0x04
52 #define	CHIPC_CORECTRL			0x08	/* rev >= 1 */
53 #define	CHIPC_BIST			0x0C
54 
55 #define	CHIPC_OTPST			0x10	/**< otp status */
56 #define	CHIPC_OTPCTRL			0x14	/**< otp control */
57 #define	CHIPC_OTPPROG			0x18
58 #define	CHIPC_OTPLAYOUT			0x1C	/**< otp layout (IPX OTP) */
59 
60 #define	CHIPC_INTST			0x20	/**< interrupt status */
61 #define	CHIPC_INTM			0x24	/**< interrupt mask */
62 
63 #define	CHIPC_CHIPCTRL			0x28	/**< chip control (rev >= 11) */
64 #define	CHIPC_CHIPST			0x2C	/**< chip status (rev >= 11) */
65 
66 #define	CHIPC_JTAGCMD			0x30
67 #define	CHIPC_JTAGIR			0x34
68 #define	CHIPC_JTAGDR			0x38
69 #define	CHIPC_JTAGCTRL			0x3c
70 
71 #define	CHIPC_SFLASH_BASE		0x40
72 #define	CHIPC_SFLASH_SIZE		12
73 #define	CHIPC_SFLASHCTRL		0x40
74 #define	CHIPC_SFLASHADDR		0x44
75 #define	CHIPC_SFLASHDATA		0x48
76 
77 /* siba backplane configuration broadcast (siba-only) */
78 #define	CHIPC_SBBCAST_ADDR		0x50
79 #define	CHIPC_SBBCAST_DATA		0x54
80 
81 #define	CHIPC_GPIOPU			0x58	/**< pull-up mask (rev >= 20) */
82 #define	CHIPC_GPIOPD			0x5C	/**< pull down mask (rev >= 20) */
83 #define	CHIPC_GPIOIN			0x60
84 #define	CHIPC_GPIOOUT			0x64
85 #define	CHIPC_GPIOOUTEN			0x68
86 #define	CHIPC_GPIOCTRL			0x6C
87 #define	CHIPC_GPIOPOL			0x70
88 #define	CHIPC_GPIOINTM			0x74	/**< gpio interrupt mask */
89 
90 #define	CHIPC_GPIOEVENT			0x78	/**< gpio event (rev >= 11) */
91 #define	CHIPC_GPIOEVENT_INTM		0x7C	/**< gpio event interrupt mask (rev >= 11) */
92 
93 #define	CHIPC_WATCHDOG			0x80	/**< watchdog timer */
94 
95 #define	CHIPC_GPIOEVENT_INTPOLARITY	0x84	/**< gpio even interrupt polarity (rev >= 11) */
96 
97 #define	CHIPC_GPIOTIMERVAL		0x88	/**< gpio-based LED duty cycle (rev >= 16) */
98 #define	CHIPC_GPIOTIMEROUTMASK		0x8C
99 
100 /* clock control registers (non-PMU devices) */
101 #define	CHIPC_CLKC_N			0x90
102 #define	CHIPC_CLKC_SB			0x94	/* m0 (backplane) */
103 #define	CHIPC_CLKC_PCI			0x98	/* m1 */
104 #define	CHIPC_CLKC_M2			0x9C	/* mii/uart/mipsref */
105 #define	CHIPC_CLKC_M3			0xA0	/* cpu */
106 #define	CHIPC_CLKDIV			0xA4	/* rev >= 3 */
107 
108 #define	CHIPC_GPIODEBUGSEL		0xA8	/* rev >= 28 */
109 #define	CHIPC_CAPABILITIES_EXT		0xAC
110 
111 /* pll/slowclk clock control registers (rev >= 4) */
112 #define	CHIPC_PLL_ON_DELAY		0xB0	/* rev >= 4 */
113 #define	CHIPC_PLL_FREFSEL_DELAY		0xB4	/* rev >= 4 */
114 #define	CHIPC_PLL_SLOWCLK_CTL		0xB8	/* "slowclock" (rev 6-9) */
115 
116  /* "instaclock" clock control registers */
117 #define	CHIPC_SYS_CLK_CTL		0xC0	/* "instaclock" (rev >= 10) */
118 #define	CHIPC_SYS_CLK_ST_STRETCH	0xC4	/* state strech (?) rev >= 10 */
119 
120 /* indirect backplane access (rev >= 10) */
121 #define	CHIPC_BP_ADDRLOW		0xD0
122 #define	CHIPC_BP_ADDRHIGH		0xD4
123 #define	CHIPC_BP_DATA			0xD8
124 #define	CHIPC_BP_INDACCESS		0xE0
125 
126 /* SPI/I2C (rev >= 37) */
127 #define	CHIPC_GSIO_CTRL			0xE4
128 #define	CHIPC_GSIO_ADDR			0xE8
129 #define	CHIPC_GSIO_DATA			0xEC
130 
131 /* More clock dividers (corerev >= 32) */
132 #define	CHIPC_CLKDIV2			0xF0
133 
134 #define	CHIPC_EROMPTR			0xFC	/**< 32-bit EROM base address
135 						  *  on BCMA devices */
136 
137 /* ExtBus control registers (rev >= 3) */
138 #define	CHIPC_PCMCIA_CFG		0x100
139 #define	CHIPC_PCMCIA_MEMWAIT		0x104
140 #define	CHIPC_PCMCIA_ATTRWAIT		0x108
141 #define	CHIPC_PCMCIA_IOWAIT		0x10C
142 #define	CHIPC_IDE_CFG			0x110
143 #define	CHIPC_IDE_MEMWAIT		0x114
144 #define	CHIPC_IDE_ATTRWAIT		0x118
145 #define	CHIPC_IDE_IOWAIT		0x11C
146 #define	CHIPC_PROG_CFG			0x120
147 #define	CHIPC_PROG_WAITCOUNT		0x124
148 #define	CHIPC_FLASH_CFG			0x128
149 #define	CHIPC_FLASH_WAITCOUNT		0x12C
150 #define	CHIPC_SECI_CFG			0x130
151 #define	CHIPC_SECI_ST			0x134
152 #define	CHIPC_SECI_STM			0x138
153 #define	CHIPC_SECI_RXNBC		0x13C
154 
155 /* Enhanced Coexistence Interface (ECI) registers (rev 21-34) */
156 #define	CHIPC_ECI_OUTPUT		0x140
157 #define	CHIPC_ECI_CTRL			0x144
158 #define	CHIPC_ECI_INPUTLO		0x148
159 #define	CHIPC_ECI_INPUTMI		0x14C
160 #define	CHIPC_ECI_INPUTHI		0x150
161 #define	CHIPC_ECI_INPUTINTPOLARITYLO	0x154
162 #define	CHIPC_ECI_INPUTINTPOLARITYMI	0x158
163 #define	CHIPC_ECI_INPUTINTPOLARITYHI	0x15C
164 #define	CHIPC_ECI_INTMASKLO		0x160
165 #define	CHIPC_ECI_INTMASKMI		0x164
166 #define	CHIPC_ECI_INTMASKHI		0x168
167 #define	CHIPC_ECI_EVENTLO		0x16C
168 #define	CHIPC_ECI_EVENTMI		0x170
169 #define	CHIPC_ECI_EVENTHI		0x174
170 #define	CHIPC_ECI_EVENTMASKLO		0x178
171 #define	CHIPC_ECI_EVENTMASKMI		0x17C
172 #define	CHIPC_ECI_EVENTMASKHI		0x180
173 
174 #define	CHIPC_FLASHSTRCFG		0x18C	/**< BCM4706 NAND flash config */
175 
176 #define	CHIPC_SPROM_CTRL		0x190	/**< SPROM interface (rev >= 32) */
177 #define	CHIPC_SPROM_ADDR		0x194
178 #define	CHIPC_SPROM_DATA		0x198
179 
180 /* Clock control and hardware workarounds (corerev >= 20) */
181 #define	CHIPC_CLK_CTL_ST		0x1E0
182 #define	CHIPC_SPROM_HWWAR		0x19
183 
184 #define	CHIPC_UART_BASE			0x300
185 #define	CHIPC_UART_SIZE			0x100
186 #define	CHIPC_UART_MAX			3	/**< max UART blocks */
187 #define	CHIPC_UART(_n)			(CHIPC_UART_BASE + (CHIPC_UART_SIZE*_n))
188 
189 /* PMU register block (rev >= 20) */
190 #define	CHIPC_PMU_BASE			0x600
191 #define	CHIPC_PMU_SIZE			0x70
192 
193 #define	CHIPC_SPROM_OTP			0x800	/* SPROM/OTP address space */
194 #define	CHIPC_SPROM_OTP_SIZE		0x400
195 
196 /** chipid */
197 #define	CHIPC_ID_CHIP_MASK	0x0000FFFF	/**< chip id */
198 #define	CHIPC_ID_CHIP_SHIFT	0
199 #define	CHIPC_ID_REV_MASK	0x000F0000	/**< chip revision */
200 #define	CHIPC_ID_REV_SHIFT	16
201 #define	CHIPC_ID_PKG_MASK	0x00F00000	/**< physical package ID */
202 #define	CHIPC_ID_PKG_SHIFT	20
203 #define	CHIPC_ID_NUMCORE_MASK	0x0F000000	/**< number of cores on chip (rev >= 4) */
204 #define	CHIPC_ID_NUMCORE_SHIFT	24
205 #define	CHIPC_ID_BUS_MASK	0xF0000000	/**< chip/interconnect type (BHND_CHIPTYPE_*) */
206 #define	CHIPC_ID_BUS_SHIFT	28
207 
208 /* capabilities */
209 #define	CHIPC_CAP_NUM_UART_MASK		0x00000003	/* Number of UARTs (1-3) */
210 #define	CHIPC_CAP_NUM_UART_SHIFT 	0
211 #define	CHIPC_CAP_MIPSEB		0x00000004	/* MIPS is in big-endian mode */
212 #define	CHIPC_CAP_UCLKSEL_MASK		0x00000018	/* UARTs clock select */
213 #define	CHIPC_CAP_UCLKSEL_SHIFT		3
214 #define	  CHIPC_CAP_UCLKSEL_UINTCLK	0x1		/* UARTs are driven by internal divided clock */
215 #define	CHIPC_CAP_UARTGPIO		0x00000020	/* UARTs own GPIOs 15:12 */
216 #define	CHIPC_CAP_EXTBUS_MASK		0x000000c0	/* External bus mask */
217 #define	CHIPC_CAP_EXTBUS_SHIFT		6
218 #define	  CHIPC_CAP_EXTBUS_NONE		0x0		/* No ExtBus present */
219 #define	  CHIPC_CAP_EXTBUS_FULL		0x1		/* ExtBus: PCMCIA, IDE & Prog */
220 #define	  CHIPC_CAP_EXTBUS_PROG		0x2		/* ExtBus: ProgIf only */
221 #define	CHIPC_CAP_FLASH_MASK		0x00000700	/* Type of flash */
222 #define	CHIPC_CAP_FLASH_SHIFT		8
223 #define	  CHIPC_CAP_FLASH_NONE		0x0		/* No flash */
224 #define	  CHIPC_CAP_SFLASH_ST		0x1		/* ST serial flash */
225 #define	  CHIPC_CAP_SFLASH_AT		0x2		/* Atmel serial flash */
226 #define	  CHIPC_CAP_NFLASH		0x3		/* NAND flash */
227 #define	  CHIPC_CAP_PFLASH		0x7		/* Parallel flash */
228 #define	CHIPC_CAP_PLL_MASK		0x00038000	/* Type of PLL */
229 #define	CHIPC_CAP_PLL_SHIFT		15
230 #define	CHIPC_CAP_PWR_CTL		0x00040000	/* Power/clock control */
231 #define	CHIPC_CAP_OTP_SIZE_MASK		0x00380000	/* OTP Size (0 = none) */
232 #define	CHIPC_CAP_OTP_SIZE_SHIFT	19		/* OTP Size shift */
233 #define	CHIPC_CAP_OTP_SIZE_BASE		5		/* OTP Size base */
234 #define	CHIPC_CAP_JTAGP			0x00400000	/* JTAG Master Present */
235 #define	CHIPC_CAP_ROM			0x00800000	/* Internal boot rom active */
236 #define	CHIPC_CAP_BKPLN64		0x08000000	/* 64-bit backplane */
237 #define	CHIPC_CAP_PMU			0x10000000	/* PMU Present, rev >= 20 */
238 #define	CHIPC_CAP_ECI			0x20000000	/* Enhanced Coexistence Interface */
239 #define	CHIPC_CAP_SPROM			0x40000000	/* SPROM Present, rev >= 32 */
240 #define	CHIPC_CAP_4706_NFLASH		0x80000000	/* NAND flash present, BCM4706 or chipc rev38 (BCM5357)? */
241 
242 #define	CHIPC_CAP2_SECI			0x00000001	/* SECI Present, rev >= 36 */
243 #define	CHIPC_CAP2_GSIO			0x00000002	/* GSIO (spi/i2c) present, rev >= 37 */
244 #define	CHIPC_CAP2_GCI			0x00000004	/* GCI present (rev >= ??) */
245 #define	CHIPC_CAP2_AOB			0x00000040	/* Always on Bus present (rev >= 49)
246 							 *
247 							 * If set, PMU and GCI registers
248 							 * are found in dedicated cores.
249 							 *
250 							 * This appears to be a lower power
251 							 * APB bus, bridged via ARM APB IP. */
252 
253 /*
254  * ChipStatus (Common)
255  */
256 
257 /** ChipStatus CIS/OTP/SPROM values used to advertise OTP/SPROM availability in
258  *  chipcommon revs 11-31. */
259 enum {
260 	CHIPC_CST_DEFCIS_SEL	= 0,	/**< OTP is powered up, use default CIS, no SPROM */
261 	CHIPC_CST_SPROM_SEL	= 1,	/**< OTP is powered up, SPROM is present */
262 	CHIPC_CST_OTP_SEL	= 2,	/**< OTP is powered up, no SPROM */
263 	CHIPC_CST_OTP_PWRDN	= 3	/**< OTP is powered down, SPROM is present (rev <= 22 only) */
264 };
265 
266 #define	CHIPC_CST_SPROM_OTP_SEL_R22_MASK	0x00000003	/**< chipstatus OTP/SPROM SEL value (rev 22) */
267 #define	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT	0
268 #define	CHIPC_CST_SPROM_OTP_SEL_R23_MASK	0x000000c0	/**< chipstatus OTP/SPROM SEL value (revs 23-31)
269 								  *
270 								  *  it is unknown whether this is supported on
271 								  *  any CC revs >= 32 that also vend CHIPC_CAP_*
272 								  *  constants for OTP/SPROM/NVRAM availability.
273 								  */
274 #define	CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT	6
275 
276 /* PLL type */
277 #define	CHIPC_PLL_NONE		0x0
278 #define	CHIPC_PLL_TYPE1		0x2	/* 48MHz base, 3 dividers */
279 #define	CHIPC_PLL_TYPE2		0x4	/* 48MHz, 4 dividers */
280 #define	CHIPC_PLL_TYPE3		0x6	/* 25MHz, 2 dividers */
281 #define	CHIPC_PLL_TYPE4		0x1	/* 48MHz, 4 dividers */
282 #define	CHIPC_PLL_TYPE5		0x3	/* 25MHz, 4 dividers */
283 #define	CHIPC_PLL_TYPE6		0x5	/* 100/200 or 120/240 only */
284 #define	CHIPC_PLL_TYPE7		0x7	/* 25MHz, 4 dividers */
285 
286 /* dynamic clock control defines */
287 #define	CHIPC_LPOMINFREQ	25000		/* low power oscillator min */
288 #define	CHIPC_LPOMAXFREQ	43000		/* low power oscillator max */
289 #define	CHIPC_XTALMINFREQ	19800000	/* 20 MHz - 1% */
290 #define	CHIPC_XTALMAXFREQ	20200000	/* 20 MHz + 1% */
291 #define	CHIPC_PCIMINFREQ	25000000	/* 25 MHz */
292 #define	CHIPC_PCIMAXFREQ	34000000	/* 33 MHz + fudge */
293 
294 #define	CHIPC_ILP_DIV_5MHZ	0		/* ILP = 5 MHz */
295 #define	CHIPC_ILP_DIV_1MHZ	4		/* ILP = 1 MHz */
296 
297 /* Power Control Defines */
298 #define	CHIPC_PLL_DELAY		150	/* us pll on delay */
299 #define	CHIPC_FREF_DELAY	200	/* us fref change delay */
300 #define	CHIPC_MIN_SLOW_CLK	32	/* us Slow clock period */
301 #define	CHIPC_XTAL_ON_DELAY	1000	/* us crystal power-on delay */
302 
303 /* corecontrol */
304 #define	CHIPC_UARTCLKO		0x00000001	/* Drive UART with internal clock */
305 #define	CHIPC_SE		0x00000002	/* sync clk out enable (corerev >= 3) */
306 #define	CHIPC_UARTCLKEN		0x00000008	/* enable UART Clock (corerev > = 21 */
307 
308 /* chipcontrol */
309 #define	CHIPCTRL_4321A0_DEFAULT	0x3a4
310 #define	CHIPCTRL_4321A1_DEFAULT	0x0a4
311 #define	CHIPCTRL_4321_PLL_DOWN	0x800000	/* serdes PLL down override */
312 
313 /* Fields in the otpstatus register in rev >= 21 */
314 #define	CHIPC_OTPS_OL_MASK		0x000000ff
315 #define	CHIPC_OTPS_OL_MFG		0x00000001	/* manuf row is locked */
316 #define	CHIPC_OTPS_OL_OR1		0x00000002	/* otp redundancy row 1 is locked */
317 #define	CHIPC_OTPS_OL_OR2		0x00000004	/* otp redundancy row 2 is locked */
318 #define	CHIPC_OTPS_OL_GU		0x00000008	/* general use region is locked */
319 #define	CHIPC_OTPS_GUP_MASK		0x00000f00
320 #define	CHIPC_OTPS_GUP_SHIFT		8
321 #define	CHIPC_OTPS_GUP_HW		0x00000100	/* h/w subregion is programmed */
322 #define	CHIPC_OTPS_GUP_SW		0x00000200	/* s/w subregion is programmed */
323 #define	CHIPC_OTPS_GUP_CI		0x00000400	/* chipid/pkgopt subregion is programmed */
324 #define	CHIPC_OTPS_GUP_FUSE		0x00000800	/* fuse subregion is programmed */
325 #define	CHIPC_OTPS_READY		0x00001000
326 #define	CHIPC_OTPS_RV(x)		(1 << (16 + (x)))	/* redundancy entry valid */
327 #define	CHIPC_OTPS_RV_MASK		0x0fff0000
328 
329 /* IPX OTP fields in the otpcontrol register */
330 #define	CHIPC_OTPC_PROGSEL		0x00000001
331 #define	CHIPC_OTPC_PCOUNT_MASK		0x0000000e
332 #define	CHIPC_OTPC_PCOUNT_SHIFT	1
333 #define	CHIPC_OTPC_VSEL_MASK		0x000000f0
334 #define	CHIPC_OTPC_VSEL_SHIFT		4
335 #define	CHIPC_OTPC_TMM_MASK		0x00000700
336 #define	CHIPC_OTPC_TMM_SHIFT		8
337 #define	CHIPC_OTPC_ODM			0x00000800
338 #define	CHIPC_OTPC_PROGEN		0x80000000
339 
340 /* Fields in otpprog in IPX OTP and HND OTP */
341 #define	CHIPC_OTPP_COL_MASK		0x000000ff
342 #define	CHIPC_OTPP_COL_SHIFT		0
343 #define	CHIPC_OTPP_ROW_MASK		0x0000ff00
344 #define	CHIPC_OTPP_ROW_SHIFT		8
345 #define	CHIPC_OTPP_OC_MASK		0x0f000000
346 #define	CHIPC_OTPP_OC_SHIFT		24
347 #define	CHIPC_OTPP_READERR		0x10000000
348 #define	CHIPC_OTPP_VALUE_MASK		0x20000000
349 #define	CHIPC_OTPP_VALUE_SHIFT	29
350 #define	CHIPC_OTPP_START_BUSY		0x80000000
351 #define	CHIPC_OTPP_READ			0x40000000	/* HND OTP */
352 
353 /* otplayout */
354 #define	CHIPC_OTPL_SIZE_MASK		0x0000f000	/* rev >= 49 */
355 #define	CHIPC_OTPL_SIZE_SHIFT		12
356 #define	CHIPC_OTPL_GUP_MASK		0x00000FFF	/* bit offset to general use region */
357 #define	CHIPC_OTPL_GUP_SHIFT		0
358 #define	CHIPC_OTPL_CISFORMAT_NEW	0x80000000	/* rev >= 36 */
359 
360 /* Opcodes for OTPP_OC field */
361 #define	CHIPC_OTPPOC_READ		0
362 #define	CHIPC_OTPPOC_BIT_PROG		1
363 #define	CHIPC_OTPPOC_VERIFY		3
364 #define	CHIPC_OTPPOC_INIT		4
365 #define	CHIPC_OTPPOC_SET		5
366 #define	CHIPC_OTPPOC_RESET		6
367 #define	CHIPC_OTPPOC_OCST		7
368 #define	CHIPC_OTPPOC_ROW_LOCK		8
369 #define	CHIPC_OTPPOC_PRESCN_TEST	9
370 
371 /* Jtagm characteristics that appeared at a given corerev */
372 #define	CHIPC_JTAGM_CREV_OLD		10	/* Old command set, 16bit max IR */
373 #define	CHIPC_JTAGM_CREV_IRP		22	/* Able to do pause-ir */
374 #define	CHIPC_JTAGM_CREV_RTI		28	/* Able to do return-to-idle */
375 
376 /* jtagcmd */
377 #define	CHIPC_JCMD_START		0x80000000
378 #define	CHIPC_JCMD_BUSY			0x80000000
379 #define	CHIPC_JCMD_STATE_MASK		0x60000000
380 #define	CHIPC_JCMD_STATE_TLR		0x00000000	/* Test-logic-reset */
381 #define	CHIPC_JCMD_STATE_PIR		0x20000000	/* Pause IR */
382 #define	CHIPC_JCMD_STATE_PDR		0x40000000	/* Pause DR */
383 #define	CHIPC_JCMD_STATE_RTI		0x60000000	/* Run-test-idle */
384 #define	CHIPC_JCMD0_ACC_MASK		0x0000f000
385 #define	CHIPC_JCMD0_ACC_IRDR		0x00000000
386 #define	CHIPC_JCMD0_ACC_DR		0x00001000
387 #define	CHIPC_JCMD0_ACC_IR		0x00002000
388 #define	CHIPC_JCMD0_ACC_RESET		0x00003000
389 #define	CHIPC_JCMD0_ACC_IRPDR		0x00004000
390 #define	CHIPC_JCMD0_ACC_PDR		0x00005000
391 #define	CHIPC_JCMD0_IRW_MASK		0x00000f00
392 #define	CHIPC_JCMD_ACC_MASK		0x000f0000	/* Changes for corerev 11 */
393 #define	CHIPC_JCMD_ACC_IRDR		0x00000000
394 #define	CHIPC_JCMD_ACC_DR		0x00010000
395 #define	CHIPC_JCMD_ACC_IR		0x00020000
396 #define	CHIPC_JCMD_ACC_RESET		0x00030000
397 #define	CHIPC_JCMD_ACC_IRPDR		0x00040000
398 #define	CHIPC_JCMD_ACC_PDR		0x00050000
399 #define	CHIPC_JCMD_ACC_PIR		0x00060000
400 #define	CHIPC_JCMD_ACC_IRDR_I		0x00070000	/* rev 28: return to run-test-idle */
401 #define	CHIPC_JCMD_ACC_DR_I		0x00080000	/* rev 28: return to run-test-idle */
402 #define	CHIPC_JCMD_IRW_MASK		0x00001f00
403 #define	CHIPC_JCMD_IRW_SHIFT		8
404 #define	CHIPC_JCMD_DRW_MASK		0x0000003f
405 
406 /* jtagctrl */
407 #define	CHIPC_JCTRL_FORCE_CLK		4	/* Force clock */
408 #define	CHIPC_JCTRL_EXT_EN		2	/* Enable external targets */
409 #define	CHIPC_JCTRL_EN		1	/* Enable Jtag master */
410 
411 /* Fields in clkdiv */
412 #define	CHIPC_CLKD_SFLASH		0x0f000000
413 #define	CHIPC_CLKD_SFLASH_SHIFT		24
414 #define	CHIPC_CLKD_OTP			0x000f0000
415 #define	CHIPC_CLKD_OTP_SHIFT		16
416 #define	CHIPC_CLKD_JTAG			0x00000f00
417 #define	CHIPC_CLKD_JTAG_SHIFT		8
418 #define	CHIPC_CLKD_UART			0x000000ff
419 
420 #define	CHIPC_CLKD2_SPROM		0x00000003
421 
422 /* intstatus/intmask */
423 #define	CHIPC_CI_GPIO			0x00000001	/* gpio intr */
424 #define	CHIPC_CI_EI			0x00000002	/* extif intr (corerev >= 3) */
425 #define	CHIPC_CI_TEMP			0x00000004	/* temp. ctrl intr (corerev >= 15) */
426 #define	CHIPC_CI_SIRQ			0x00000008	/* serial IRQ intr (corerev >= 15) */
427 #define	CHIPC_CI_PMU			0x00000020	/* pmu intr (corerev >= 21) */
428 #define	CHIPC_CI_UART			0x00000040	/* uart intr (corerev >= 21) */
429 #define	CHIPC_CI_WDRESET		0x80000000	/* watchdog reset occurred */
430 
431 /* slow_clk_ctl */
432 #define	CHIPC_SCC_SS_MASK		0x00000007	/* slow clock source mask */
433 #define	CHIPC_SCC_SS_LPO		0x00000000	/* source of slow clock is LPO */
434 #define	CHIPC_SCC_SS_XTAL		0x00000001	/* source of slow clock is crystal */
435 #define	CHIPC_SCC_SS_PCI		0x00000002	/* source of slow clock is PCI */
436 #define	CHIPC_SCC_LF			0x00000200	/* LPOFreqSel, 1: 160Khz, 0: 32KHz */
437 #define	CHIPC_SCC_LP			0x00000400	/* LPOPowerDown, 1: LPO is disabled,
438 						 * 0: LPO is enabled
439 						 */
440 #define	CHIPC_SCC_FS			0x00000800	/* ForceSlowClk, 1: sb/cores running on slow clock,
441 						 * 0: power logic control
442 						 */
443 #define	CHIPC_SCC_IP			0x00001000	/* IgnorePllOffReq, 1/0: power logic ignores/honors
444 						 * PLL clock disable requests from core
445 						 */
446 #define	CHIPC_SCC_XC			0x00002000	/* XtalControlEn, 1/0: power logic does/doesn't
447 						 * disable crystal when appropriate
448 						 */
449 #define	CHIPC_SCC_XP			0x00004000	/* XtalPU (RO), 1/0: crystal running/disabled */
450 #define	CHIPC_SCC_CD_MASK		0xffff0000	/* ClockDivider (SlowClk = 1/(4+divisor)) */
451 #define	CHIPC_SCC_CD_SHIFT		16
452 
453 /* system_clk_ctl */
454 #define	CHIPC_SYCC_IE			0x00000001	/* ILPen: Enable Idle Low Power */
455 #define	CHIPC_SYCC_AE			0x00000002	/* ALPen: Enable Active Low Power */
456 #define	CHIPC_SYCC_FP			0x00000004	/* ForcePLLOn */
457 #define	CHIPC_SYCC_AR			0x00000008	/* Force ALP (or HT if ALPen is not set */
458 #define	CHIPC_SYCC_HR			0x00000010	/* Force HT */
459 #define	CHIPC_SYCC_CD_MASK		0xffff0000	/* ClkDiv  (ILP = 1/(4 * (divisor + 1)) */
460 #define	CHIPC_SYCC_CD_SHIFT		16
461 
462 /* Indirect backplane access */
463 #define	CHIPC_BPIA_BYTEEN		0x0000000f
464 #define	CHIPC_BPIA_SZ1			0x00000001
465 #define	CHIPC_BPIA_SZ2			0x00000003
466 #define	CHIPC_BPIA_SZ4			0x00000007
467 #define	CHIPC_BPIA_SZ8			0x0000000f
468 #define	CHIPC_BPIA_WRITE		0x00000100
469 #define	CHIPC_BPIA_START		0x00000200
470 #define	CHIPC_BPIA_BUSY			0x00000200
471 #define	CHIPC_BPIA_ERROR		0x00000400
472 
473 /* pcmcia/prog/flash_config */
474 #define	CHIPC_CF_EN			0x00000001	/* enable */
475 #define	CHIPC_CF_EM_MASK		0x0000000e	/* mode */
476 #define	CHIPC_CF_EM_SHIFT		1
477 #define	CHIPC_CF_EM_FLASH		0	/* flash/asynchronous mode */
478 #define	CHIPC_CF_EM_SYNC		2	/* synchronous mode */
479 #define	CHIPC_CF_EM_PCMCIA		4	/* pcmcia mode */
480 #define	CHIPC_CF_DS			0x00000010	/* destsize:  0=8bit, 1=16bit */
481 #define	CHIPC_CF_BS			0x00000020	/* byteswap */
482 #define	CHIPC_CF_CD_MASK		0x000000c0	/* clock divider */
483 #define	CHIPC_CF_CD_SHIFT		6
484 #define	CHIPC_CF_CD_DIV2		0x00000000	/* backplane/2 */
485 #define	CHIPC_CF_CD_DIV3		0x00000040	/* backplane/3 */
486 #define	CHIPC_CF_CD_DIV4		0x00000080	/* backplane/4 */
487 #define	CHIPC_CF_CE			0x00000100	/* clock enable */
488 #define	CHIPC_CF_SB			0x00000200	/* size/bytestrobe (synch only) */
489 
490 /* pcmcia_memwait */
491 #define	CHIPC_PM_W0_MASK		0x0000003f	/* waitcount0 */
492 #define	CHIPC_PM_W1_MASK		0x00001f00	/* waitcount1 */
493 #define	CHIPC_PM_W1_SHIFT		8
494 #define	CHIPC_PM_W2_MASK		0x001f0000	/* waitcount2 */
495 #define	CHIPC_PM_W2_SHIFT		16
496 #define	CHIPC_PM_W3_MASK		0x1f000000	/* waitcount3 */
497 #define	CHIPC_PM_W3_SHIFT		24
498 
499 /* pcmcia_attrwait */
500 #define	CHIPC_PA_W0_MASK		0x0000003f	/* waitcount0 */
501 #define	CHIPC_PA_W1_MASK		0x00001f00	/* waitcount1 */
502 #define	CHIPC_PA_W1_SHIFT		8
503 #define	CHIPC_PA_W2_MASK		0x001f0000	/* waitcount2 */
504 #define	CHIPC_PA_W2_SHIFT		16
505 #define	CHIPC_PA_W3_MASK		0x1f000000	/* waitcount3 */
506 #define	CHIPC_PA_W3_SHIFT		24
507 
508 /* pcmcia_iowait */
509 #define	CHIPC_PI_W0_MASK		0x0000003f	/* waitcount0 */
510 #define	CHIPC_PI_W1_MASK		0x00001f00	/* waitcount1 */
511 #define	CHIPC_PI_W1_SHIFT		8
512 #define	CHIPC_PI_W2_MASK		0x001f0000	/* waitcount2 */
513 #define	CHIPC_PI_W2_SHIFT		16
514 #define	CHIPC_PI_W3_MASK		0x1f000000	/* waitcount3 */
515 #define	CHIPC_PI_W3_SHIFT		24
516 
517 /* prog_waitcount */
518 #define	CHIPC_PW_W0_MASK		0x0000001f	/* waitcount0 */
519 #define	CHIPC_PW_W1_MASK		0x00001f00	/* waitcount1 */
520 #define	CHIPC_PW_W1_SHIFT		8
521 #define	CHIPC_PW_W2_MASK		0x001f0000	/* waitcount2 */
522 #define	CHIPC_PW_W2_SHIFT		16
523 #define	CHIPC_PW_W3_MASK		0x1f000000	/* waitcount3 */
524 #define	CHIPC_PW_W3_SHIFT		24
525 
526 #define	CHIPC_PW_W0       		0x0000000c
527 #define	CHIPC_PW_W1       		0x00000a00
528 #define	CHIPC_PW_W2       		0x00020000
529 #define	CHIPC_PW_W3       		0x01000000
530 
531 /* flash_waitcount */
532 #define	CHIPC_FW_W0_MASK		0x0000003f	/* waitcount0 */
533 #define	CHIPC_FW_W1_MASK		0x00001f00	/* waitcount1 */
534 #define	CHIPC_FW_W1_SHIFT		8
535 #define	CHIPC_FW_W2_MASK		0x001f0000	/* waitcount2 */
536 #define	CHIPC_FW_W2_SHIFT		16
537 #define	CHIPC_FW_W3_MASK		0x1f000000	/* waitcount3 */
538 #define	CHIPC_FW_W3_SHIFT		24
539 
540 /* When SPROM support present, fields in spromcontrol */
541 #define	CHIPC_SRC_START			0x80000000
542 #define	CHIPC_SRC_BUSY			0x80000000
543 #define	CHIPC_SRC_OPCODE		0x60000000
544 #define	CHIPC_SRC_OP_READ		0x00000000
545 #define	CHIPC_SRC_OP_WRITE		0x20000000
546 #define	CHIPC_SRC_OP_WRDIS		0x40000000
547 #define	CHIPC_SRC_OP_WREN		0x60000000
548 #define	CHIPC_SRC_OTPSEL		0x00000010
549 #define	CHIPC_SRC_LOCK			0x00000008
550 #define	CHIPC_SRC_SIZE_MASK		0x00000006
551 #define	CHIPC_SRC_SIZE_1K		0x00000000
552 #define	CHIPC_SRC_SIZE_4K		0x00000002
553 #define	CHIPC_SRC_SIZE_16K		0x00000004
554 #define	CHIPC_SRC_SIZE_SHIFT		1
555 #define	CHIPC_SRC_PRESENT		0x00000001
556 
557 /* gpiotimerval */
558 #define	CHIPC_GPIO_ONTIME_SHIFT		16
559 #define	CHIPC_GPIOTIMERVAL_DEFAULT_ON	10	/**< default 10% on duty cycle */
560 #define	CHIPC_GPIOTIMERVAL_DEFAULT_OFF	90	/**< default 90% off duty cycle */
561 #define	CHIPC_GPIOTIMERVAL_DEFAULT					\
562     ((CHIPC_GPIOTIMERVAL_DEFAULT_ON << CHIPC_GPIO_ONTIME_SHIFT) |	\
563      (CHIPC_GPIOTIMERVAL_DEFAULT_OFF))
564 
565 /* clockcontrol_n */
566 #define	CHIPC_CN_N1_MASK		0x3f	/* n1 control */
567 #define	CHIPC_CN_N1_SHIFT		0
568 #define	CHIPC_CN_N2_MASK		0x3f00	/* n2 control */
569 #define	CHIPC_CN_N2_SHIFT		8
570 #define	CHIPC_CN_PLLC_MASK		0xf0000	/* pll control */
571 #define	CHIPC_CN_PLLC_SHIFT		16
572 
573 /* clockcontrol_sb/pci/uart */
574 #define	CHIPC_M1_MASK		0x3f	/* m1 control */
575 #define	CHIPC_M1_SHIFT		0
576 #define	CHIPC_M2_MASK		0x3f00	/* m2 control */
577 #define	CHIPC_M2_SHIFT		8
578 #define	CHIPC_M3_MASK		0x3f0000	/* m3 control */
579 #define	CHIPC_M3_SHIFT		16
580 #define	CHIPC_MC_MASK		0x1f000000	/* mux control */
581 #define	CHIPC_MC_SHIFT		24
582 
583 /* N3M Clock control magic field values */
584 #define	CHIPC_F6_2		0x02	/* A factor of 2 in */
585 #define	CHIPC_F6_3		0x03	/* 6-bit fields like */
586 #define	CHIPC_F6_4		0x05	/* N1, M1 or M3 */
587 #define	CHIPC_F6_5		0x09
588 #define	CHIPC_F6_6		0x11
589 #define	CHIPC_F6_7		0x21
590 
591 #define	CHIPC_F5_BIAS		5	/* 5-bit fields get this added */
592 
593 #define	CHIPC_MC_BYPASS		0x08
594 #define	CHIPC_MC_M1		0x04
595 #define	CHIPC_MC_M1M2		0x02
596 #define	CHIPC_MC_M1M2M3		0x01
597 #define	CHIPC_MC_M1M3		0x11
598 
599 /* Type 2 Clock control magic field values */
600 #define	CHIPC_T2_BIAS		2	/* n1, n2, m1 & m3 bias */
601 #define	CHIPC_T2M2_BIAS		3	/* m2 bias */
602 
603 #define	CHIPC_T2MC_M1BYP	1
604 #define	CHIPC_T2MC_M2BYP	2
605 #define	CHIPC_T2MC_M3BYP	4
606 
607 /* Type 6 Clock control magic field values */
608 #define	CHIPC_T6_MMASK		1	/* bits of interest in m */
609 #define	CHIPC_T6_M0		120000000	/* sb clock for m = 0 */
610 #define	CHIPC_T6_M1		100000000	/* sb clock for m = 1 */
611 #define	CHIPC_SB2MIPS_T6(sb)	(2 * (sb))
612 
613 /* Common clock base */
614 #define	CHIPC_CLOCK_BASE1	24000000	/* Half the clock freq */
615 #define	CHIPC_CLOCK_BASE2	12500000	/* Alternate crystal on some PLLs */
616 
617 /* Clock control values for 200MHz in 5350 */
618 #define	CHIPC_CLKC_5350_N	0x0311
619 #define	CHIPC_CLKC_5350_M	0x04020009
620 
621 /* Bits in the ExtBus config registers */
622 #define	CHIPC_CFG_EN		0x0001	/* Enable */
623 #define	CHIPC_CFG_EM_MASK	0x000e	/* Extif Mode */
624 #define	CHIPC_CFG_EM_ASYNC	0x0000	/*   Async/Parallel flash */
625 #define	CHIPC_CFG_EM_SYNC	0x0002	/*   Synchronous */
626 #define	CHIPC_CFG_EM_PCMCIA	0x0004	/*   PCMCIA */
627 #define	CHIPC_CFG_EM_IDE	0x0006	/*   IDE */
628 #define	CHIPC_FLASH_CFG_DS	0x0010	/* Data size, 0=8bit, 1=16bit */
629 #define	CHIPC_FLASH_CFG_CD_MASK	0x00e0	/* Sync: Clock divisor, rev >= 20 */
630 #define	CHIPC_FLASH_CFG_CE	0x0100	/* Sync: Clock enable, rev >= 20 */
631 #define	CHIPC_FLASH_CFG_SB	0x0200	/* Sync: Size/Bytestrobe, rev >= 20 */
632 #define	CHIPC_FLASH_CFG_IS	0x0400	/* Extif Sync Clk Select, rev >= 20 */
633 
634 /* ExtBus address space */
635 #define	CHIPC_EB_BASE		0x1a000000	/* Chipc ExtBus base address */
636 #define	CHIPC_EB_PCMCIA_MEM	0x1a000000	/* PCMCIA 0 memory base address */
637 #define	CHIPC_EB_PCMCIA_IO	0x1a200000	/* PCMCIA 0 I/O base address */
638 #define	CHIPC_EB_PCMCIA_CFG	0x1a400000	/* PCMCIA 0 config base address */
639 #define	CHIPC_EB_IDE		0x1a800000	/* IDE memory base */
640 #define	CHIPC_EB_PCMCIA1_MEM	0x1a800000	/* PCMCIA 1 memory base address */
641 #define	CHIPC_EB_PCMCIA1_IO	0x1aa00000	/* PCMCIA 1 I/O base address */
642 #define	CHIPC_EB_PCMCIA1_CFG	0x1ac00000	/* PCMCIA 1 config base address */
643 #define	CHIPC_EB_PROGIF		0x1b000000	/* ProgIF Async/Sync base address */
644 
645 /* Start/busy bit in flashcontrol */
646 #define	CHIPC_SFLASH_OPCODE	0x000000ff
647 #define	CHIPC_SFLASH_ACTION	0x00000700
648 #define	CHIPC_SFLASH_CS_ACTIVE	0x00001000	/* Chip Select Active, rev >= 20 */
649 #define	CHIPC_SFLASH_START	0x80000000
650 #define	CHIPC_SFLASH_BUSY	SFLASH_START
651 
652 /* flashcontrol action codes */
653 #define	CHIPC_SFLASH_ACT_OPONLY		0x0000	/* Issue opcode only */
654 #define	CHIPC_SFLASH_ACT_OP1D		0x0100	/* opcode + 1 data byte */
655 #define	CHIPC_SFLASH_ACT_OP3A		0x0200	/* opcode + 3 addr bytes */
656 #define	CHIPC_SFLASH_ACT_OP3A1D		0x0300	/* opcode + 3 addr & 1 data bytes */
657 #define	CHIPC_SFLASH_ACT_OP3A4D		0x0400	/* opcode + 3 addr & 4 data bytes */
658 #define	CHIPC_SFLASH_ACT_OP3A4X4D	0x0500	/* opcode + 3 addr, 4 don't care & 4 data bytes */
659 #define	CHIPC_SFLASH_ACT_OP3A1X4D	0x0700	/* opcode + 3 addr, 1 don't care & 4 data bytes */
660 
661 /* flashcontrol action+opcodes for ST flashes */
662 #define	CHIPC_SFLASH_ST_WREN		0x0006	/* Write Enable */
663 #define	CHIPC_SFLASH_ST_WRDIS		0x0004	/* Write Disable */
664 #define	CHIPC_SFLASH_ST_RDSR		0x0105	/* Read Status Register */
665 #define	CHIPC_SFLASH_ST_WRSR		0x0101	/* Write Status Register */
666 #define	CHIPC_SFLASH_ST_READ		0x0303	/* Read Data Bytes */
667 #define	CHIPC_SFLASH_ST_PP		0x0302	/* Page Program */
668 #define	CHIPC_SFLASH_ST_SE		0x02d8	/* Sector Erase */
669 #define	CHIPC_SFLASH_ST_BE		0x00c7	/* Bulk Erase */
670 #define	CHIPC_SFLASH_ST_DP		0x00b9	/* Deep Power-down */
671 #define	CHIPC_SFLASH_ST_RES		0x03ab	/* Read Electronic Signature */
672 #define	CHIPC_SFLASH_ST_CSA		0x1000	/* Keep chip select asserted */
673 #define	CHIPC_SFLASH_ST_SSE		0x0220	/* Sub-sector Erase */
674 
675 /* Status register bits for ST flashes */
676 #define	CHIPC_SFLASH_ST_WIP		0x01	/* Write In Progress */
677 #define	CHIPC_SFLASH_ST_WEL		0x02	/* Write Enable Latch */
678 #define	CHIPC_SFLASH_ST_BP_MASK		0x1c	/* Block Protect */
679 #define	CHIPC_SFLASH_ST_BP_SHIFT	2
680 #define	CHIPC_SFLASH_ST_SRWD		0x80	/* Status Register Write Disable */
681 
682 /* flashcontrol action+opcodes for Atmel flashes */
683 #define	CHIPC_SFLASH_AT_READ				0x07e8
684 #define	CHIPC_SFLASH_AT_PAGE_READ			0x07d2
685 #define	CHIPC_SFLASH_AT_BUF1_READ
686 #define	CHIPC_SFLASH_AT_BUF2_READ
687 #define	CHIPC_SFLASH_AT_STATUS				0x01d7
688 #define	CHIPC_SFLASH_AT_BUF1_WRITE			0x0384
689 #define	CHIPC_SFLASH_AT_BUF2_WRITE			0x0387
690 #define	CHIPC_SFLASH_AT_BUF1_ERASE_PROGRAM		0x0283
691 #define	CHIPC_SFLASH_AT_BUF2_ERASE_PROGRAM		0x0286
692 #define	CHIPC_SFLASH_AT_BUF1_PROGRAM			0x0288
693 #define	CHIPC_SFLASH_AT_BUF2_PROGRAM			0x0289
694 #define	CHIPC_SFLASH_AT_PAGE_ERASE			0x0281
695 #define	CHIPC_SFLASH_AT_BLOCK_ERASE			0x0250
696 #define	CHIPC_SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM	0x0382
697 #define	CHIPC_SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM	0x0385
698 #define	CHIPC_SFLASH_AT_BUF1_LOAD			0x0253
699 #define	CHIPC_SFLASH_AT_BUF2_LOAD			0x0255
700 #define	CHIPC_SFLASH_AT_BUF1_COMPARE			0x0260
701 #define	CHIPC_SFLASH_AT_BUF2_COMPARE			0x0261
702 #define	CHIPC_SFLASH_AT_BUF1_REPROGRAM			0x0258
703 #define	CHIPC_SFLASH_AT_BUF2_REPROGRAM			0x0259
704 
705 /* Status register bits for Atmel flashes */
706 #define	CHIPC_SFLASH_AT_READY				0x80
707 #define	CHIPC_SFLASH_AT_MISMATCH			0x40
708 #define	CHIPC_SFLASH_AT_ID_MASK				0x38
709 #define	CHIPC_SFLASH_AT_ID_SHIFT			3
710 
711 /*
712  * These are the UART port assignments, expressed as offsets from the base
713  * register.  These assignments should hold for any serial port based on
714  * a 8250, 16450, or 16550(A).
715  */
716 
717 #define	CHIPC_UART_RX			0	/* In:  Receive buffer (DLAB=0) */
718 #define	CHIPC_UART_TX			0	/* Out: Transmit buffer (DLAB=0) */
719 #define	CHIPC_UART_DLL			0	/* Out: Divisor Latch Low (DLAB=1) */
720 #define	CHIPC_UART_IER			1	/* In/Out: Interrupt Enable Register (DLAB=0) */
721 #define	CHIPC_UART_DLM			1	/* Out: Divisor Latch High (DLAB=1) */
722 #define	CHIPC_UART_IIR			2	/* In: Interrupt Identity Register  */
723 #define	CHIPC_UART_FCR			2	/* Out: FIFO Control Register */
724 #define	CHIPC_UART_LCR			3	/* Out: Line Control Register */
725 #define	CHIPC_UART_MCR			4	/* Out: Modem Control Register */
726 #define	CHIPC_UART_LSR			5	/* In:  Line Status Register */
727 #define	CHIPC_UART_MSR			6	/* In:  Modem Status Register */
728 #define	CHIPC_UART_SCR			7	/* I/O: Scratch Register */
729 #define	CHIPC_UART_LCR_DLAB		0x80	/* Divisor latch access bit */
730 #define	CHIPC_UART_LCR_WLEN8		0x03	/* Word length: 8 bits */
731 #define	CHIPC_UART_MCR_OUT2		0x08	/* MCR GPIO out 2 */
732 #define	CHIPC_UART_MCR_LOOP		0x10	/* Enable loopback test mode */
733 #define	CHIPC_UART_LSR_RX_FIFO 		0x80	/* Receive FIFO error */
734 #define	CHIPC_UART_LSR_TDHR		0x40	/* Data-hold-register empty */
735 #define	CHIPC_UART_LSR_THRE		0x20	/* Transmit-hold-register empty */
736 #define	CHIPC_UART_LSR_BREAK		0x10	/* Break interrupt */
737 #define	CHIPC_UART_LSR_FRAMING		0x08	/* Framing error */
738 #define	CHIPC_UART_LSR_PARITY		0x04	/* Parity error */
739 #define	CHIPC_UART_LSR_OVERRUN		0x02	/* Overrun error */
740 #define	CHIPC_UART_LSR_RXRDY		0x01	/* Receiver ready */
741 #define	CHIPC_UART_FCR_FIFO_ENABLE	1	/* FIFO control register bit controlling FIFO enable/disable */
742 
743 /* Interrupt Identity Register (IIR) bits */
744 #define	CHIPC_UART_IIR_FIFO_MASK	0xc0	/* IIR FIFO disable/enabled mask */
745 #define	CHIPC_UART_IIR_INT_MASK		0xf	/* IIR interrupt ID source */
746 #define	CHIPC_UART_IIR_MDM_CHG		0x0	/* Modem status changed */
747 #define	CHIPC_UART_IIR_NOINT		0x1	/* No interrupt pending */
748 #define	CHIPC_UART_IIR_THRE		0x2	/* THR empty */
749 #define	CHIPC_UART_IIR_RCVD_DATA	0x4	/* Received data available */
750 #define	CHIPC_UART_IIR_RCVR_STATUS 	0x6	/* Receiver status */
751 #define	CHIPC_UART_IIR_CHAR_TIME 	0xc	/* Character time */
752 
753 /* Interrupt Enable Register (IER) bits */
754 #define	CHIPC_UART_IER_EDSSI	8	/* enable modem status interrupt */
755 #define	CHIPC_UART_IER_ELSI	4	/* enable receiver line status interrupt */
756 #define	CHIPC_UART_IER_ETBEI	2	/* enable transmitter holding register empty interrupt */
757 #define	CHIPC_UART_IER_ERBFI	1	/* enable data available interrupt */
758 
759 /* 4325 chip-specific ChipStatus register bits */
760 #define	CHIPC_CST4325_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R22_MASK
761 #define	CHIPC_CST4325_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
762 #define	CHIPC_CST4325_SDIO_USB_MODE_MASK	0x00000004
763 #define	CHIPC_CST4325_SDIO_USB_MODE_SHIFT	2
764 #define	CHIPC_CST4325_RCAL_VALID_MASK		0x00000008
765 #define	CHIPC_CST4325_RCAL_VALID_SHIFT		3
766 #define	CHIPC_CST4325_RCAL_VALUE_MASK		0x000001f0
767 #define	CHIPC_CST4325_RCAL_VALUE_SHIFT		4
768 #define	CHIPC_CST4325_PMUTOP_2B_MASK 		0x00000200	/* 1 for 2b, 0 for to 2a */
769 #define	CHIPC_CST4325_PMUTOP_2B_SHIFT   	9
770 
771 /* 4329 chip-specific ChipStatus register bits */
772 #define	CHIPC_CST4329_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R22_MASK
773 #define	CHIPC_CST4329_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
774 #define	CHIPC_CST4329_SPI_SDIO_MODE_MASK	0x00000004
775 #define	CHIPC_CST4329_SPI_SDIO_MODE_SHIFT	2
776 
777 /* 4312 chip-specific ChipStatus register bits */
778 #define	CHIPC_CST4312_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R22_MASK
779 #define	CHIPC_CST4312_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
780 
781 /* 4322 chip-specific ChipStatus register bits */
782 #define	CHIPC_CST4322_XTAL_FREQ_20_40MHZ	0x00000020
783 #define	CHIPC_CST4322_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R23_MASK
784 #define	CHIPC_CST4322_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT
785 #define	CHIPC_CST4322_PCI_OR_USB		0x00000100
786 #define	CHIPC_CST4322_BOOT_MASK			0x00000600
787 #define	CHIPC_CST4322_BOOT_SHIFT		9
788 #define	CHIPC_CST4322_BOOT_FROM_SRAM		0	/* boot from SRAM, ARM in reset */
789 #define	CHIPC_CST4322_BOOT_FROM_ROM		1	/* boot from ROM */
790 #define	CHIPC_CST4322_BOOT_FROM_FLASH		2	/* boot from FLASH */
791 #define	CHIPC_CST4322_BOOT_FROM_INVALID		3
792 #define	CHIPC_CST4322_ILP_DIV_EN		0x00000800
793 #define	CHIPC_CST4322_FLASH_TYPE_MASK		0x00001000
794 #define	CHIPC_CST4322_FLASH_TYPE_SHIFT		12
795 #define	CHIPC_CST4322_FLASH_TYPE_SHIFT_ST	0	/* ST serial FLASH */
796 #define	CHIPC_CST4322_FLASH_TYPE_SHIFT_ATMEL	1	/* ATMEL flash */
797 #define	CHIPC_CST4322_ARM_TAP_SEL		0x00002000
798 #define	CHIPC_CST4322_RES_INIT_MODE_MASK	0x0000c000
799 #define	CHIPC_CST4322_RES_INIT_MODE_SHIFT	14
800 #define	CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL	0	/* resinitmode: ILP available */
801 #define	CHIPC_CST4322_RES_INIT_MODE_ILPREQ	1	/* resinitmode: ILP request */
802 #define	CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL	2	/* resinitmode: ALP available */
803 #define	CHIPC_CST4322_RES_INIT_MODE_HTAVAIL	3	/* resinitmode: HT available */
804 #define	CHIPC_CST4322_PCIPLLCLK_GATING		0x00010000
805 #define	CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP	0x00020000
806 #define	CHIPC_CST4322_PCI_CARDBUS_MODE		0x00040000
807 
808 /* 43236 Chip specific ChipStatus register bits */
809 #define	CHIPC_CST43236_SFLASH_MASK		0x00000040
810 #define	CHIPC_CST43236_OTP_SEL_MASK		0x00000080
811 #define	CHIPC_CST43236_OTP_SEL_SHIFT		7
812 #define	CHIPC_CST43236_HSIC_MASK		0x00000100	/* USB/HSIC */
813 #define	CHIPC_CST43236_BP_CLK			0x00000200	/* 120/96Mbps */
814 #define	CHIPC_CST43236_BOOT_MASK		0x00001800
815 #define	CHIPC_CST43236_BOOT_SHIFT		11
816 #define	CHIPC_CST43236_BOOT_FROM_SRAM		0	/* boot from SRAM, ARM in reset */
817 #define	CHIPC_CST43236_BOOT_FROM_ROM		1	/* boot from ROM */
818 #define	CHIPC_CST43236_BOOT_FROM_FLASH		2	/* boot from FLASH */
819 #define	CHIPC_CST43236_BOOT_FROM_INVALID	3
820 
821 /* 43237 Chip specific ChipStatus register bits */
822 #define	CHIPC_CST43237_BP_CLK			0x00000200	/* 96/80Mbps */
823 
824 /* 4331 Chip specific ChipStatus register bits */
825 #define	CHIPC_CST4331_XTAL_FREQ			0x00000001	/* crystal frequency 20/40Mhz */
826 #define	CHIPC_CST4331_SPROM_PRESENT		0x00000002
827 #define	CHIPC_CST4331_OTP_PRESENT		0x00000004
828 #define	CHIPC_CST4331_LDO_RF			0x00000008
829 #define	CHIPC_CST4331_LDO_PAR			0x00000010
830 
831 /* 4331 chip-specific CHIPCTRL register bits */
832 #define	CHIPC_CCTRL4331_BT_COEXIST		(1<<0)	/* 0 disable */
833 #define	CHIPC_CCTRL4331_SECI			(1<<1)	/* 0 SECI is disabled (JATG functional) */
834 #define	CHIPC_CCTRL4331_EXT_LNA			(1<<2)	/* 0 disable */
835 #define	CHIPC_CCTRL4331_SPROM_GPIO13_15		(1<<3)	/* sprom/gpio13-15 mux */
836 #define	CHIPC_CCTRL4331_EXTPA_EN		(1<<4)	/* 0 ext pa disable, 1 ext pa enabled */
837 #define	CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS	(1<<5)	/* set drive out GPIO_CLK on sprom_cs pin */
838 #define	CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS	(1<<6)	/* use sprom_cs pin as PCIE mdio interface */
839 #define	CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5	(1<<7)	/* aband extpa will be at gpio2/5 and sprom_dout */
840 #define	CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN	(1<<8)	/* override core control on pipe_AuxClkEnable */
841 #define	CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN	(1<<9)	/* override core control on pipe_AuxPowerDown */
842 #define	CHIPC_CCTRL4331_PCIE_AUXCLKEN		(1<<10)	/* pcie_auxclkenable */
843 #define	CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN	(1<<11)	/* pcie_pipe_pllpowerdown */
844 #define	CHIPC_CCTRL4331_EXTPA_EN2		(1<<12)	/* 0 ext pa2 disable, 1 ext pa2 enabled */
845 #define	CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4	(1<<16)	/* enable bt_shd0 at gpio4 */
846 #define	CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5	(1<<17)	/* enable bt_shd1 at gpio5 */
847 
848 /* 4315 chip-specific ChipStatus register bits */
849 #define	CHIPC_CST4315_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R22_MASK
850 #define	CHIPC_CST4315_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT
851 #define	CHIPC_CST4315_SDIO_MODE			0x00000004	/* gpio [8], sdio/usb mode */
852 #define	CHIPC_CST4315_RCAL_VALID		0x00000008
853 #define	CHIPC_CST4315_RCAL_VALUE_MASK		0x000001f0
854 #define	CHIPC_CST4315_RCAL_VALUE_SHIFT		4
855 #define	CHIPC_CST4315_PALDO_EXTPNP		0x00000200	/* PALDO is configured with external PNP */
856 #define	CHIPC_CST4315_CBUCK_MODE_MASK		0x00000c00
857 #define	CHIPC_CST4315_CBUCK_MODE_BURST		0x00000400
858 #define	CHIPC_CST4315_CBUCK_MODE_LPBURST	0x00000c00
859 
860 /* 4319 chip-specific ChipStatus register bits */
861 #define	CHIPC_CST4319_SPI_CPULESSUSB		0x00000001
862 #define	CHIPC_CST4319_SPI_CLK_POL		0x00000002
863 #define	CHIPC_CST4319_SPI_CLK_PH		0x00000008
864 #define	CHIPC_CST4319_SPROM_OTP_SEL_MASK	CHIPC_CST_SPROM_OTP_SEL_R23_MASK	/* gpio [7:6], SDIO CIS selection */
865 #define	CHIPC_CST4319_SPROM_OTP_SEL_SHIFT	CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT
866 #define	CHIPC_CST4319_SDIO_USB_MODE		0x00000100	/* gpio [8], sdio/usb mode */
867 #define	CHIPC_CST4319_REMAP_SEL_MASK		0x00000600
868 #define	CHIPC_CST4319_ILPDIV_EN			0x00000800
869 #define	CHIPC_CST4319_XTAL_PD_POL		0x00001000
870 #define	CHIPC_CST4319_LPO_SEL			0x00002000
871 #define	CHIPC_CST4319_RES_INIT_MODE		0x0000c000
872 #define	CHIPC_CST4319_PALDO_EXTPNP		0x00010000	/* PALDO is configured with external PNP */
873 #define	CHIPC_CST4319_CBUCK_MODE_MASK		0x00060000
874 #define	CHIPC_CST4319_CBUCK_MODE_BURST		0x00020000
875 #define	CHIPC_CST4319_CBUCK_MODE_LPBURST	0x00060000
876 #define	CHIPC_CST4319_RCAL_VALID		0x01000000
877 #define	CHIPC_CST4319_RCAL_VALUE_MASK		0x3e000000
878 #define	CHIPC_CST4319_RCAL_VALUE_SHIFT		25
879 
880 /* 4336 chip-specific ChipStatus register bits */
881 #define	CHIPC_CST4336_SPI_MODE_MASK		0x00000001
882 #define	CHIPC_CST4336_SPROM_PRESENT		0x00000002
883 #define	CHIPC_CST4336_OTP_PRESENT		0x00000004
884 #define	CHIPC_CST4336_ARMREMAP_0		0x00000008
885 #define	CHIPC_CST4336_ILPDIV_EN_MASK		0x00000010
886 #define	CHIPC_CST4336_ILPDIV_EN_SHIFT		4
887 #define	CHIPC_CST4336_XTAL_PD_POL_MASK		0x00000020
888 #define	CHIPC_CST4336_XTAL_PD_POL_SHIFT		5
889 #define	CHIPC_CST4336_LPO_SEL_MASK		0x00000040
890 #define	CHIPC_CST4336_LPO_SEL_SHIFT		6
891 #define	CHIPC_CST4336_RES_INIT_MODE_MASK	0x00000180
892 #define	CHIPC_CST4336_RES_INIT_MODE_SHIFT	7
893 #define	CHIPC_CST4336_CBUCK_MODE_MASK		0x00000600
894 #define	CHIPC_CST4336_CBUCK_MODE_SHIFT		9
895 
896 /* 4330 chip-specific ChipStatus register bits */
897 #define	CHIPC_CST4330_CHIPMODE_SDIOD(cs)	(((cs) & 0x7) < 6)	/* SDIO || gSPI */
898 #define	CHIPC_CST4330_CHIPMODE_USB20D(cs)	(((cs) & 0x7) >= 6)	/* USB || USBDA */
899 #define	CHIPC_CST4330_CHIPMODE_SDIO(cs)		(((cs) & 0x4) == 0)	/* SDIO */
900 #define	CHIPC_CST4330_CHIPMODE_GSPI(cs)		(((cs) & 0x6) == 4)	/* gSPI */
901 #define	CHIPC_CST4330_CHIPMODE_USB(cs)		(((cs) & 0x7) == 6)	/* USB packet-oriented */
902 #define	CHIPC_CST4330_CHIPMODE_USBDA(cs)	(((cs) & 0x7) == 7)	/* USB Direct Access */
903 #define	CHIPC_CST4330_OTP_PRESENT		0x00000010
904 #define	CHIPC_CST4330_LPO_AUTODET_EN		0x00000020
905 #define	CHIPC_CST4330_ARMREMAP_0		0x00000040
906 #define	CHIPC_CST4330_SPROM_PRESENT		0x00000080	/* takes priority over OTP if both set */
907 #define	CHIPC_CST4330_ILPDIV_EN			0x00000100
908 #define	CHIPC_CST4330_LPO_SEL			0x00000200
909 #define	CHIPC_CST4330_RES_INIT_MODE_SHIFT	10
910 #define	CHIPC_CST4330_RES_INIT_MODE_MASK	0x00000c00
911 #define	CHIPC_CST4330_CBUCK_MODE_SHIFT		12
912 #define	CHIPC_CST4330_CBUCK_MODE_MASK		0x00003000
913 #define	CHIPC_CST4330_CBUCK_POWER_OK		0x00004000
914 #define	CHIPC_CST4330_BB_PLL_LOCKED		0x00008000
915 #define	CHIPC_SOCDEVRAM_4330_BP_ADDR		0x1E000000
916 #define	CHIPC_SOCDEVRAM_4330_ARM_ADDR		0x00800000
917 
918 /* 4313 chip-specific ChipStatus register bits */
919 #define	CHIPC_CST4313_SPROM_PRESENT		1
920 #define	CHIPC_CST4313_OTP_PRESENT		2
921 #define	CHIPC_CST4313_SPROM_OTP_SEL_MASK	0x00000002
922 #define	CHIPC_CST4313_SPROM_OTP_SEL_SHIFT	0
923 
924 /* 43228 chipstatus  reg bits */
925 #define	CHIPC_CST43228_ILP_DIV_EN		0x1
926 #define	CHIPC_CST43228_OTP_PRESENT		0x2
927 #define	CHIPC_CST43228_SERDES_REFCLK_PADSEL	0x4
928 #define	CHIPC_CST43228_SDIO_MODE		0x8
929 
930 #define	CHIPC_CST43228_SDIO_OTP_PRESENT		0x10
931 #define	CHIPC_CST43228_SDIO_RESET		0x20
932 
933 /* 4706 chipstatus reg bits */
934 #define	CHIPC_CST4706_LOWCOST_PKG		(1<<0)	/* 0: full-featured package 1: low-cost package */
935 #define	CHIPC_CST4706_SFLASH_PRESENT		(1<<1)	/* 0: parallel, 1: serial flash is present */
936 #define	CHIPC_CST4706_SFLASH_TYPE		(1<<2)	/* 0: 8b-p/ST-s flash, 1: 16b-p/Atmal-s flash */
937 #define	CHIPC_CST4706_MIPS_BENDIAN		(1<<3)	/* 0: little,  1: big endian */
938 #define	CHIPC_CST4706_PCIE1_DISABLE		(1<<5)	/* PCIE1 enable strap pin */
939 
940 /* 4706 flashstrconfig reg bits */
941 #define	CHIPC_FLSTRCF4706_MASK			0x000000ff
942 #define	CHIPC_FLSTRCF4706_SF1			0x00000001      /* 2nd serial flash present */
943 #define	CHIPC_FLSTRCF4706_PF1			0x00000002      /* 2nd parallel flash present */
944 #define	CHIPC_FLSTRCF4706_SF1_TYPE		0x00000004      /* 2nd serial flash type : 0 : ST, 1 : Atmel */
945 #define	CHIPC_FLSTRCF4706_NF1			0x00000008      /* 2nd NAND flash present */
946 #define	CHIPC_FLSTRCF4706_1ST_MADDR_SEG_MASK	0x000000f0      /* Valid value mask */
947 #define	CHIPC_FLSTRCF4706_1ST_MADDR_SEG_SHIFT	4
948 #define	  CHIPC_FLSTRCF4706_1ST_MADDR_SEG_4MB	0x1		/* 4MB */
949 #define	  CHIPC_FLSTRCF4706_1ST_MADDR_SEG_8MB	0x2		/* 8MB */
950 #define	  CHIPC_FLSTRCF4706_1ST_MADDR_SEG_16MB	0x3		/* 16MB */
951 #define	  CHIPC_FLSTRCF4706_1ST_MADDR_SEG_32MB	0x4		/* 32MB */
952 #define	  CHIPC_FLSTRCF4706_1ST_MADDR_SEG_64MB	0x5		/* 64MB */
953 #define	  CHIPC_FLSTRCF4706_1ST_MADDR_SEG_128MB	0x6		/* 128MB */
954 #define	  CHIPC_FLSTRCF4706_1ST_MADDR_SEG_256MB	0x7		/* 256MB */
955 
956 /*
957 * Register eci_inputlo bitfield values.
958 * - BT packet type information bits [7:0]
959 */
960 /*  [3:0] - Task (link) type */
961 #define	CHIPC_BT_ACL				0x00
962 #define	CHIPC_BT_SCO				0x01
963 #define	CHIPC_BT_eSCO				0x02
964 #define	CHIPC_BT_A2DP				0x03
965 #define	CHIPC_BT_SNIFF				0x04
966 #define	CHIPC_BT_PAGE_SCAN			0x05
967 #define	CHIPC_BT_INQUIRY_SCAN			0x06
968 #define	CHIPC_BT_PAGE				0x07
969 #define	CHIPC_BT_INQUIRY			0x08
970 #define	CHIPC_BT_MSS				0x09
971 #define	CHIPC_BT_PARK				0x0a
972 #define	CHIPC_BT_RSSISCAN			0x0b
973 #define	CHIPC_BT_MD_ACL				0x0c
974 #define	CHIPC_BT_MD_eSCO			0x0d
975 #define	CHIPC_BT_SCAN_WITH_SCO_LINK		0x0e
976 #define	CHIPC_BT_SCAN_WITHOUT_SCO_LINK		0x0f
977 /* [7:4] = packet duration code */
978 /* [8] - Master / Slave */
979 #define	CHIPC_BT_MASTER				0
980 #define	CHIPC_BT_SLAVE				1
981 /* [11:9] - multi-level priority */
982 #define	CHIPC_BT_LOWEST_PRIO			0x0
983 #define	CHIPC_BT_HIGHEST_PRIO			0x3
984 
985 #endif /* _BHND_CORES_CHIPC_CHIPCREG_H_ */
986