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Searched refs:BuildMI (Results 1 – 25 of 350) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp178 BuildMI(LoopMBB, DL, in doAtomicBinOpExpansion()
186 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
191 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
194 BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg) in doAtomicBinOpExpansion()
199 BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg) in doAtomicBinOpExpansion()
204 BuildMI(LoopMBB, DL, TII->get(LoongArch::SUB_W), ScratchReg) in doAtomicBinOpExpansion()
209 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
214 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
219 BuildMI(LoopMBB, DL, TII->get(LoongArch::XOR), ScratchReg) in doAtomicBinOpExpansion()
224 BuildMI(LoopMBB, DL, in doAtomicBinOpExpansion()
[all …]
H A DLoongArchExpandPseudoInsts.cpp196 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg) in expandPcalau12iInstPair()
200 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg) in expandPcalau12iInstPair()
283 auto Part1 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), TmpPart1); in expandLargeAddressLoad()
284 auto Part0 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADDI_D), TmpPart0) in expandLargeAddressLoad()
286 auto Part2 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), TmpParts02) in expandLargeAddressLoad()
289 auto Part3 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), TmpParts023) in expandLargeAddressLoad()
291 BuildMI(MBB, MBBI, DL, TII->get(LastOpcode), DestReg) in expandLargeAddressLoad()
378 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU12I_W), Part1) in expandLoadAddressTLSLE()
384 BuildMI(MBB, MBBI, DL, TII->get(AddOp), Parts01) in expandLoadAddressTLSLE()
390 BuildMI(MBB, MBBI, DL, TII->get(AddiOp), DestReg) in expandLoadAddressTLSLE()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp144 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
145 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2) in expandAtomicCmpSwapSubword()
148 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwapSubword()
156 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch) in expandAtomicCmpSwapSubword()
159 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch) in expandAtomicCmpSwapSubword()
162 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwapSubword()
166 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
174 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
178 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest); in expandAtomicCmpSwapSubword()
182 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest) in expandAtomicCmpSwapSubword()
[all …]
H A DMipsBranchExpansion.cpp344 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
400 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
469 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
472 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
493 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
498 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
500 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
515 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
518 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
530 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
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H A DMipsInstructionSelector.cpp262 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
276 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedLoad()
302 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
326 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) in select()
333 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) in select()
343 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
355 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
368 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) in select()
376 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
385 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp197 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg); in selectIntToFP()
205 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); in selectIntToFP()
222 BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg); in selectFPToInt()
232 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg); in selectFPToInt()
235 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); in selectFPToInt()
254 BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF), in selectZExt()
259 BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::INSERT_SUBREG), in selectZExt()
266 BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg) in selectZExt()
305 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), Reg) in selectI64ImmDirect()
311 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Reg) in selectI64ImmDirect()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCExpandAtomicPseudoInsts.cpp56 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
57 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
58 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
62 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
159 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
167 BuildMI(CurrentMBB, DL, TII->get(PPC::ADDC8), ScratchLo) in expandAtomicRMW128()
170 BuildMI(CurrentMBB, DL, TII->get(PPC::ADDE8), ScratchHi) in expandAtomicRMW128()
[all …]
H A DPPCFrameLowering.cpp797 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg); in emitPrologue()
801 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg); in emitPrologue()
811 BuildMI(MBB, MBBI, dl, StoreWordInst) in emitPrologue()
818 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); in emitPrologue()
825 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
830 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
835 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
846 BuildMI(MBB, StackUpdateLoc, dl, StoreInst) in emitPrologue()
864 BuildMI(MBB, StackUpdateLoc, dl, HashST) in emitPrologue()
877 BuildMI(MBB, MBBI, dl, StoreWordInst) in emitPrologue()
[all …]
H A DPPCTLSDynamicCall.cpp161 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0) in processBlock()
249 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3) in processBlock()
252 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3); in processBlock()
257 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4) in processBlock()
259 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3) in processBlock()
261 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4); in processBlock()
266 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3); in processBlock()
270 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0); in processBlock()
274 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg); in processBlock()
280 (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3)); in processBlock()
[all …]
H A DPPCRegisterInfo.cpp770 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1) in lowerDynamicAlloc()
774 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
778 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1) in lowerDynamicAlloc()
782 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
831 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), FramePointer) in prepareDynamicAlloca()
835 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) in prepareDynamicAlloca()
839 BuildMI(MBB, II, dl, TII.get(PPC::LD), FramePointer) in prepareDynamicAlloca()
843 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), FramePointer) in prepareDynamicAlloca()
855 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg) in prepareDynamicAlloca()
860 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg) in prepareDynamicAlloca()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp167 MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(TBB); in insertBranch()
175 MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).addMBB(TBB); in insertBranch()
184 MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(FBB); in insertBranch()
238 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI32), DstReg) in movImm()
242 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
246 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
249 BuildMI(MBB, MBBI, DL, get(CSKY::ORI32), DstReg) in movImm()
258 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
262 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
265 BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg) in movImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp149 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
154 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
161 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
166 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
173 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
197 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17) in emitEpilogueInsns()
202 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16) in emitEpilogueInsns()
206 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15) in emitEpilogueInsns()
212 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10) in emitEpilogueInsns()
216 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9) in emitEpilogueInsns()
[all …]
H A DVEInstrInfo.cpp237 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
269 BuildMI(&MBB, DL, get(opc[0])) in insertBranch()
275 BuildMI(&MBB, DL, get(opc[1])) in insertBranch()
285 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
341 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); in copyPhysSubRegs()
346 BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc); in copyPhysSubRegs()
364 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
377 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) in copyPhysReg()
381 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) in copyPhysReg()
387 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp37 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
40 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
79 BuildMI(*BB, MI, dl, get(LdOpc)) in expandMEMCPY()
82 BuildMI(*BB, MI, dl, get(StOpc)) in expandMEMCPY()
93 BuildMI(*BB, MI, dl, get(BPF::LDW)) in expandMEMCPY()
95 BuildMI(*BB, MI, dl, get(BPF::STW)) in expandMEMCPY()
100 BuildMI(*BB, MI, dl, get(BPF::LDH)) in expandMEMCPY()
102 BuildMI(*BB, MI, dl, get(BPF::STH)) in expandMEMCPY()
107 BuildMI(*BB, MI, dl, get(BPF::LDB)) in expandMEMCPY()
109 BuildMI(*BB, MI, dl, get(BPF::STB)) in expandMEMCPY()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp275 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg) in doAtomicBinOpExpansion()
281 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in doAtomicBinOpExpansion()
284 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in doAtomicBinOpExpansion()
289 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg) in doAtomicBinOpExpansion()
292 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in doAtomicBinOpExpansion()
309 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg) in insertMaskedMerge()
312 BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg) in insertMaskedMerge()
315 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
344 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering, STI)), DestReg) in doMaskedAtomicBinOpExpansion()
350 BuildMI(LoopMBB, DL, TII->get(RISCV::ADDI), ScratchReg) in doMaskedAtomicBinOpExpansion()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp61 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
69 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
73 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), STI.getTmpRegister()) in emitPrologue()
76 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
80 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
83 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
107 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
124 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitPrologue()
132 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitPrologue()
151 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), STI.getZeroRegister()); in restoreStatusRegister()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp243 BuildMI(MBB, MBBI, DL, TII.get(X86::TRAP)); in emitSPUpdate()
260 BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset); in emitSPUpdate()
277 BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Uses64BitFramePtr, Offset)), in emitSPUpdate()
281 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr) in emitSPUpdate()
295 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r)) in emitSPUpdate()
304 BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Uses64BitFramePtr, Offset)), in emitSPUpdate()
308 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax) in emitSPUpdate()
314 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax), in emitSPUpdate()
317 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr), in emitSPUpdate()
333 BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp155 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
163 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
176 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
187 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
195 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
208 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
219 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
266 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::MOVZWi), StatusReg) in expandCMP_SWAP()
268 BuildMI(LoadCmpBB, MIMD, TII->get(LdarOp), Dest.getReg()) in expandCMP_SWAP()
270 BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
[all …]
H A DAArch64PointerAuth.cpp64 BuildMI(MBB, I, DL, TII.get(AArch64::ADRP), AArch64::X16) in emitPACSymOffsetIntoX16()
66 BuildMI(MBB, I, DL, TII.get(AArch64::ADDXri), AArch64::X16) in emitPACSymOffsetIntoX16()
91 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACM)).setMIFlag(Flags); in BuildPACM()
120 BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY)) in signLR()
135 BuildMI(MBB, MBBI, DL, in signLR()
144 BuildMI(MBB, MBBI, DL, in signLR()
154 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PACSignLR)) in signLR()
189 BuildMI(MBB, TI, DL, in authenticateLR()
196 BuildMI(MBB, TI, DL, TII->get(UseBKey ? AArch64::RETAB : AArch64::RETAA)) in authenticateLR()
206 BuildMI(MBB, MBBI, DL, in authenticateLR()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h373 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, in BuildMI() function
382 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, in BuildMI() function
393 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
412 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
425 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, in BuildMI() function
431 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), MIMD, MCID, in BuildMI()
433 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID, DestReg); in BuildMI()
436 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, in BuildMI() function
439 return BuildMI(BB, *I, MIMD, MCID, DestReg); in BuildMI()
445 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMExpandPseudoInsts.cpp561 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD()
679 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVST()
756 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandLaneOp()
841 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); in ExpandVTBL()
880 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMQQPRLoadStore()
1021 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg) in ExpandTMOV32BitImm()
1035 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Op), DstReg) in ExpandTMOV32BitImm()
1082 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
1083 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
1089 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); in ExpandMOV32BitImm()
[all …]
H A DARMFrameLowering.cpp453 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
462 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags()); in insertSEH()
471 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags); in insertSEH()
476 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
489 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
493 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
503 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
517 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
560 BuildMI(MF, DL, TII.get(NewOpc)).setMIFlags(MBBI->getFlags()); in insertSEH()
569 MIB = BuildMI(MF, DL, TII.get(SEHOpc)) in insertSEH()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr) in generateStackAdjustment()
141 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
147 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9)) in emitPrologue()
158 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
159 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6)) in emitPrologue()
163 BuildMI(MBB, MBBI, dl, TII->get(ARC::BL)) in emitPrologue()
172 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
185 BuildMI(MBB, MBBI, dl, in emitPrologue()
199 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
207 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaFrameLowering.cpp68 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::ENTRY)) in emitPrologue()
75 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::ENTRY)) in emitPrologue()
79 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::SUB), TmpReg) in emitPrologue()
82 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::MOVSP), SP).addReg(TmpReg); in emitPrologue()
95 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::AND)) in emitPrologue()
99 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::SUB), RegMisAlign) in emitPrologue()
102 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::ADD), SP) in emitPrologue()
110 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::OR), Xtensa::A8) in emitPrologue()
118 BuildMI(MBB, MBBI, DL, TII.get(Xtensa::OR), FP) in emitPrologue()
126 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp586 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc)); in createHalfInstr()
640 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first) in splitMemRef()
643 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second) in splitMemRef()
649 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
653 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
667 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR) in splitMemRef()
710 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first) in splitImmediate()
712 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitImmediate()
730 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitCombine()
733 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second) in splitCombine()
[all …]

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