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Searched refs:BuildMI (Results 1 – 25 of 340) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchExpandAtomicPseudoInsts.cpp162 BuildMI(LoopMBB, DL, in doAtomicBinOpExpansion()
170 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
175 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
178 BuildMI(LoopMBB, DL, TII->get(LoongArch::NOR), ScratchReg) in doAtomicBinOpExpansion()
183 BuildMI(LoopMBB, DL, TII->get(LoongArch::ADD_W), ScratchReg) in doAtomicBinOpExpansion()
188 BuildMI(LoopMBB, DL, TII->get(LoongArch::SUB_W), ScratchReg) in doAtomicBinOpExpansion()
193 BuildMI(LoopMBB, DL, TII->get(LoongArch::AND), ScratchReg) in doAtomicBinOpExpansion()
198 BuildMI(LoopMBB, DL, TII->get(LoongArch::OR), ScratchReg) in doAtomicBinOpExpansion()
203 BuildMI(LoopMBB, DL, TII->get(LoongArch::XOR), ScratchReg) in doAtomicBinOpExpansion()
208 BuildMI(LoopMB in doAtomicBinOpExpansion()
[all...]
H A DLoongArchExpandPseudoInsts.cpp147 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg) in expandPcalau12iInstPair()
151 BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg) in expandPcalau12iInstPair()
212 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU12I_W), Part1) in expandLoadAddressTLSLE()
215 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ORI), Parts01) in expandLoadAddressTLSLE()
223 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), Parts012) in expandLoadAddressTLSLE()
227 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), DestReg) in expandLoadAddressTLSLE()
298 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg) in expandLoadAddressTLSDesc()
301 BuildMI(MBB, MBBI, DL, TII->get(ADDI), LoongArch::R4) in expandLoadAddressTLSDesc()
305 BuildMI(MBB, MBBI, DL, TII->get(LD), LoongArch::R1) in expandLoadAddressTLSDesc()
309 BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PseudoDESC_CALL), LoongArch::R1) in expandLoadAddressTLSDesc()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsExpandPseudo.cpp145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0); in expandAtomicCmpSwapSubword()
146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2) in expandAtomicCmpSwapSubword()
149 BuildMI(loop1MBB, DL, TII->get(BNE)) in expandAtomicCmpSwapSubword()
157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch) in expandAtomicCmpSwapSubword()
160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch) in expandAtomicCmpSwapSubword()
163 BuildMI(loop2MBB, DL, TII->get(SC), Scratch) in expandAtomicCmpSwapSubword()
167 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest) in expandAtomicCmpSwapSubword()
179 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest); in expandAtomicCmpSwapSubword()
183 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest) in expandAtomicCmpSwapSubword()
[all …]
H A DMipsBranchExpansion.cpp344 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc); in replaceBranch()
400 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg); in buildProperJumpMI()
469 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
472 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)) in expandToLongBranch()
493 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT) in expandToLongBranch()
498 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB); in expandToLongBranch()
500 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT) in expandToLongBranch()
515 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
518 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA) in expandToLongBranch()
530 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP) in expandToLongBranch()
[all …]
H A DMipsSEFrameLowering.cpp178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst) in expandLoadCCond()
192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR) in expandStoreCCond()
216 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill); in expandLoadACC()
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
238 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandStoreACC()
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
272 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src); in expandCopyACC()
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo) in expandCopyACC()
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi) in expandCopyACC()
[all …]
H A DMipsInstructionSelector.cpp262 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedStore()
276 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opc)) in buildUnalignedLoad()
302 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL)) in select()
326 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu)) in select()
333 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI)) in select()
343 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
355 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu)) in select()
368 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL)) in select()
376 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
385 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW)) in select()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/GISel/
H A DPPCInstructionSelector.cpp197 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MTVSRD), MoveReg).addReg(SrcReg); in selectIntToFP()
205 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), DstReg).addReg(MoveReg); in selectIntToFP()
222 BuildMI(MBB, I, DbgLoc, TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg); in selectFPToInt()
232 BuildMI(MBB, I, DbgLoc, TII.get(ConvOp), ConvReg).addReg(CopyReg); in selectFPToInt()
235 BuildMI(MBB, I, DbgLoc, TII.get(PPC::MFVSRD), DstReg).addReg(ConvReg); in selectFPToInt()
254 BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF), in selectZExt()
259 BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::INSERT_SUBREG), in selectZExt()
266 BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::RLDICL), DstReg) in selectZExt()
305 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LI8), Reg) in selectI64ImmDirect()
311 return BuildMI(MBB, I, I.getDebugLoc(), TII.get(PPC::LIS8), Reg) in selectI64ImmDirect()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo.cpp167 MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(TBB); in insertBranch()
175 MachineInstr &CondMI = *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).addMBB(TBB); in insertBranch()
184 MachineInstr &MI = *BuildMI(&MBB, DL, get(CSKY::BR32)).addMBB(FBB); in insertBranch()
238 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI32), DstReg) in movImm()
242 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
246 BuildMI(MBB, MBBI, DL, get(CSKY::MOVIH32), DstReg) in movImm()
249 BuildMI(MBB, MBBI, DL, get(CSKY::ORI32), DstReg) in movImm()
258 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
262 BuildMI(MBB, MBBI, DL, get(CSKY::MOVI16), DstReg) in movImm()
265 BuildMI(MBB, MBBI, DL, get(CSKY::LSLI16), DstReg) in movImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp797 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFOCRF8), TempReg); in emitPrologue()
801 BuildMI(MBB, MBBI, dl, MoveFromCondRegInst, TempReg); in emitPrologue()
811 BuildMI(MBB, MBBI, dl, StoreWordInst) in emitPrologue()
818 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg); in emitPrologue()
825 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
830 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
835 BuildMI(MBB, MBBI, dl, StoreInst) in emitPrologue()
846 BuildMI(MBB, StackUpdateLoc, dl, StoreInst) in emitPrologue()
864 BuildMI(MBB, StackUpdateLoc, dl, HashST) in emitPrologue()
877 BuildMI(MBB, MBBI, dl, StoreWordInst) in emitPrologue()
[all …]
H A DPPCExpandAtomicPseudoInsts.cpp59 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
60 BuildMI(MBB, MBBI, DL, XOR, Dest1).addReg(Dest0).addReg(Dest1); in PairedCopy()
61 BuildMI(MBB, MBBI, DL, XOR, Dest0).addReg(Dest0).addReg(Dest1); in PairedCopy()
64 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
65 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
67 BuildMI(MBB, MBBI, DL, OR, Dest0).addReg(Src0).addReg(Src0); in PairedCopy()
68 BuildMI(MBB, MBBI, DL, OR, Dest1).addReg(Src1).addReg(Src1); in PairedCopy()
162 BuildMI(CurrentMBB, DL, LL, Old).addReg(RA).addReg(RB); in expandAtomicRMW128()
170 BuildMI(CurrentMBB, DL, TII->get(PPC::ADDC8), ScratchLo) in expandAtomicRMW128()
173 BuildMI(CurrentMBB, DL, TII->get(PPC::ADDE8), ScratchHi) in expandAtomicRMW128()
[all …]
H A DPPCTLSDynamicCall.cpp165 BuildMI(MBB, I, DL, TII->get(PPC::ADJCALLSTACKDOWN)).addImm(0) in processBlock()
253 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3) in processBlock()
256 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3); in processBlock()
261 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR4) in processBlock()
263 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), GPR3) in processBlock()
265 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3).addReg(GPR4); in processBlock()
270 BuildMI(MBB, I, DL, TII->get(Opc2), GPR3); in processBlock()
274 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addImm(0); in processBlock()
278 Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3).addReg(InReg); in processBlock()
284 (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3).addReg(GPR3)); in processBlock()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVExpandAtomicPseudoInsts.cpp277 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width, STI)), DestReg) in insertMaskedMerge()
283 BuildMI(LoopMBB, DL, TII->get(RISCV::AND), ScratchReg) in insertMaskedMerge()
286 BuildMI(LoopMBB, DL, TII->get(RISCV::XORI), ScratchReg) in insertMaskedMerge()
291 BuildMI(LoopMBB, DL, TII->get(getSCForRMW(Ordering, Width, STI)), ScratchReg) in insertMaskedMerge()
294 BuildMI(LoopMBB, DL, TII->get(RISCV::BNE)) in insertMaskedMerge()
311 BuildMI(MBB, DL, TII->get(RISCV::XOR), ScratchReg) in doMaskedAtomicBinOpExpansion()
314 BuildMI(MBB, DL, TII->get(RISCV::AND), ScratchReg) in doMaskedAtomicBinOpExpansion()
317 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in doMaskedAtomicBinOpExpansion()
346 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering, STI)), DestReg) in doMaskedAtomicBinOpExpansion()
352 BuildMI(LoopMB in doMaskedAtomicBinOpExpansion()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEFrameLowering.cpp152 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
157 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
164 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
169 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
176 BuildMI(MBB, MBBI, DL, TII.get(VE::STrii)) in emitPrologueInsns()
200 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX17) in emitEpilogueInsns()
205 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX16) in emitEpilogueInsns()
209 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX15) in emitEpilogueInsns()
215 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX10) in emitEpilogueInsns()
219 BuildMI(MBB, MBBI, DL, TII.get(VE::LDrii), VE::SX9) in emitEpilogueInsns()
[all …]
H A DVEInstrInfo.cpp238 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
270 BuildMI(&MBB, DL, get(opc[0])) in insertBranch()
276 BuildMI(&MBB, DL, get(opc[1])) in insertBranch()
286 BuildMI(&MBB, DL, get(VE::BRCFLa_t)) in insertBranch()
342 BuildMI(MBB, I, DL, MCID, SubDest).addReg(SubSrc).addImm(0); in copyPhysSubRegs()
347 BuildMI(MBB, I, DL, MCID, SubDest).addReg(VE::VM0).addReg(SubSrc); in copyPhysSubRegs()
365 BuildMI(MBB, I, DL, get(VE::ORri), DestReg) in copyPhysReg()
378 BuildMI(MBB, I, DL, get(VE::LEAzii), TmpReg) in copyPhysReg()
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(VE::VORmvl), DestReg) in copyPhysReg()
388 BuildMI(MBB, I, DL, get(VE::ANDMmm), DestReg) in copyPhysReg()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64PointerAuth.cpp87 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ADR)) in BuildPACM()
95 BuildMI(MBB, MBBI, DL, TII->get(AArch64::PACM)).setMIFlag(Flags); in BuildPACM()
112 BuildMI(MBB, MBBI, DL, TII->get(AArch64::EMITBKEY)) in signLR()
126 BuildMI(MBB, MBBI, DL, in signLR()
133 BuildMI(MBB, MBBI, DL, in signLR()
155 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION)) in signLR()
159 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SEH_PACSignLR)) in signLR()
193 BuildMI(MBB, TI, DL, in authenticateLR()
200 BuildMI(MBB, TI, DL, TII->get(UseBKey ? AArch64::RETAB : AArch64::RETAA)) in authenticateLR()
208 BuildMI(MBB, MBBI, DL, in authenticateLR()
[all …]
H A DAArch64ExpandPseudoInsts.cpp155 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
163 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
176 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
187 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
195 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
208 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
219 MIBS.push_back(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(I->Opcode)) in expandMOVImm()
266 BuildMI(LoadCmpBB, MIMD, TII->get(AArch64::MOVZWi), StatusReg) in expandCMP_SWAP()
268 BuildMI(LoadCmpBB, MIMD, TII->get(LdarOp), Dest.getReg()) in expandCMP_SWAP()
270 BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFInstrInfo.cpp36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg) in copyPhysReg()
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg) in copyPhysReg()
78 BuildMI(*BB, MI, dl, get(LdOpc)) in expandMEMCPY()
81 BuildMI(*BB, MI, dl, get(StOpc)) in expandMEMCPY()
92 BuildMI(*BB, MI, dl, get(BPF::LDW)) in expandMEMCPY()
94 BuildMI(*BB, MI, dl, get(BPF::STW)) in expandMEMCPY()
99 BuildMI(*BB, MI, dl, get(BPF::LDH)) in expandMEMCPY()
101 BuildMI(*BB, MI, dl, get(BPF::STH)) in expandMEMCPY()
106 BuildMI(*BB, MI, dl, get(BPF::LDB)) in expandMEMCPY()
108 BuildMI(*BB, MI, dl, get(BPF::STB)) in expandMEMCPY()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRFrameLowering.cpp62 BuildMI(MBB, MBBI, DL, TII.get(AVR::BSETs)) in emitPrologue()
70 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
74 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), STI.getTmpRegister()) in emitPrologue()
77 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
81 BuildMI(MBB, MBBI, DL, TII.get(AVR::PUSHRr)) in emitPrologue()
84 BuildMI(MBB, MBBI, DL, TII.get(AVR::EORRdRr)) in emitPrologue()
108 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28) in emitPrologue()
125 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28) in emitPrologue()
133 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP) in emitPrologue()
152 BuildMI(MB in restoreStatusRegister()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FrameLowering.cpp251 BuildMI(MBB, MBBI, DL, TII.get(X86::STACKALLOC_W_PROBING)).addImm(Offset); in emitSPUpdate()
267 BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Offset)), Reg) in emitSPUpdate()
270 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr) in emitSPUpdate()
284 BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH64r)) in emitSPUpdate()
293 BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Offset)), Rax) in emitSPUpdate()
296 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax) in emitSPUpdate()
302 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax), in emitSPUpdate()
305 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr), in emitSPUpdate()
321 BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate()
367 MI = addRegOffset(BuildMI(MBB, MBBI, DL, in BuildStackAdjustment()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFrameLowering.cpp316 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
325 BuildMI(MF, DL, TII.get(ARM::tMOVi8)).setMIFlags(MBBI->getFlags()); in insertSEH()
334 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)).addImm(Wide).setMIFlags(Flags); in insertSEH()
339 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
352 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
356 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_Nop)) in insertSEH()
366 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
380 MIB = BuildMI(MF, DL, TII.get(ARM::SEH_SaveRegs)) in insertSEH()
423 BuildMI(MF, DL, TII.get(NewOpc)).setMIFlags(MBBI->getFlags()); in insertSEH()
432 MIB = BuildMI(MF, DL, TII.get(SEHOpc)) in insertSEH()
[all …]
H A DARMExpandPseudoInsts.cpp562 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD()
680 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVST()
757 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandLaneOp()
842 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); in ExpandVTBL()
881 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); in ExpandMQQPRLoadStore()
1022 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tLSLri), DstReg) in ExpandTMOV32BitImm()
1036 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Op), DstReg) in ExpandTMOV32BitImm()
1083 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
1084 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) in ExpandMOV32BitImm()
1090 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), DstReg); in ExpandMOV32BitImm()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h373 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, in BuildMI() function
382 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, in BuildMI() function
393 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
412 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
425 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, in BuildMI() function
431 return BuildMI(BB, MachineBasicBlock::instr_iterator(I), MIMD, MCID, in BuildMI()
433 return BuildMI(BB, MachineBasicBlock::iterator(I), MIMD, MCID, DestReg); in BuildMI()
436 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I, in BuildMI() function
439 return BuildMI(BB, *I, MIMD, MCID, DestReg); in BuildMI()
445 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, in BuildMI() function
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCFrameLowering.cpp72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr) in generateStackAdjustment()
141 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP) in emitPrologue()
147 BuildMI(MBB, MBBI, dl, TII->get(ARC::ST_AW_rs9)) in emitPrologue()
158 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
159 BuildMI(MBB, MBBI, dl, TII->get(ARC::SUB_rru6)) in emitPrologue()
163 BuildMI(MBB, MBBI, dl, TII->get(ARC::BL)) in emitPrologue()
172 BuildMI(MBB, MBBI, dl, TII->get(ARC::PUSH_S_BLINK)); in emitPrologue()
185 BuildMI(MBB, MBBI, dl, in emitPrologue()
199 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
207 BuildMI(MBB, MBBI, dl, TII->get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6) in emitSPAdjustment()
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) in emitSPAdjustment()
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1) in emitSPAdjustment()
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1) in emitSPAdjustment()
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6) in emitSPAdjustment()
156 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
161 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
169 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION)) in emitPrologue()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSplitDouble.cpp592 MachineInstr *NewI = BuildMI(B, MI, DL, TII->get(Opc)); in createHalfInstr()
646 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.first) in splitMemRef()
649 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::L2_loadri_io), P.second) in splitMemRef()
655 LowI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
659 HighI = BuildMI(B, MI, DL, TII->get(Hexagon::S2_storeri_io)) in splitMemRef()
673 BuildMI(B, MI, DL, TII->get(Hexagon::A2_addi), NewR) in splitMemRef()
716 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.first) in splitImmediate()
718 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitImmediate()
736 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), P.second) in splitCombine()
739 BuildMI(B, MI, DL, TII->get(TargetOpcode::COPY), P.second) in splitCombine()
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