Searched refs:BaseDef (Results 1 – 5 of 5) sorted by relevance
478 Record *BaseDef = in addEntryWithFlags() local481 BaseDef ? Target.getInstruction(BaseDef).isMoveReg : RegInst->isMoveReg; in addEntryWithFlags()484 if (IsMoveReg && (BaseDef || Result.FoldStore)) in addEntryWithFlags()
946 MachineInstr *BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() local947 if (BaseDef && BaseDef->isPHI()) { in computeDelta()948 BaseReg = getLoopPhiReg(*BaseDef, MI.getParent()); in computeDelta()949 BaseDef = MRI.getVRegDef(BaseReg); in computeDelta()951 if (!BaseDef) in computeDelta()955 if (!TII->getIncrementValue(*BaseDef, D) && D >= 0) in computeDelta()
2587 MachineInstr *BaseDef = MRI.getVRegDef(BaseReg); in computeDelta() local2588 if (BaseDef && BaseDef->isPHI()) { in computeDelta()2589 BaseReg = getLoopPhiReg(*BaseDef, MI.getParent()); in computeDelta()2590 BaseDef = MRI.getVRegDef(BaseReg); in computeDelta()2592 if (!BaseDef) in computeDelta()2596 if (!TII->getIncrementValue(*BaseDef, D) && D >= 0) in computeDelta()
4784 std::optional<DefinitionAndSourceRegister> BaseDef = in isFlatScratchBaseLegalSVImm() local4794 if (isNoUnsignedWrap(BaseDef->MI) && in isFlatScratchBaseLegalSVImm()4800 Register LHS = BaseDef->MI->getOperand(1).getReg(); in isFlatScratchBaseLegalSVImm()4801 Register RHS = BaseDef->MI->getOperand(2).getReg(); in isFlatScratchBaseLegalSVImm()
1280 MachineInstr *BaseDef = getDefIgnoringCopies(Base, MRI); in findPreIndexCandidate() local1281 if (BaseDef->getOpcode() == TargetOpcode::G_FRAME_INDEX) in findPreIndexCandidate()