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Searched refs:Barrier (Results 1 – 25 of 33) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DLiveRangeShrink.cpp140 unsigned Barrier = 0; in runOnMachineFunction()
148 // Barrier is the last instruction where MO get used. MI should not in runOnMachineFunction()
149 // be moved above Barrier. in runOnMachineFunction()
150 if (Barrier < UseMap[MO.getReg()].first) { in runOnMachineFunction()
151 Barrier = UseMap[MO.getReg()].first; in runOnMachineFunction()
211 // If Barrier equals IOM[I], traverse forward to find if BarrierMI is in runOnMachineFunction()
213 for (MachineInstr *I = Insert; I && IOM[I] == Barrier; in runOnMachineFunction()
220 if (DefMO && Insert && NumEligibleUse > 1 && Barrier <= IOM[Insert]) { in runOnMachineFunction()
138 unsigned Barrier = 0; runOnMachineFunction() local
H A DMachinePipeliner.cpp884 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
894 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
902 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
909 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
918 SDep Dep(Load, SDep::Barrier); in addLoopCarriedDependences()
968 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
990 I.addPred(SDep(SU, SDep::Barrier)); in updatePhiDependences()
H A DScheduleDAG.cpp95 case Barrier: dbgs() << " Barrier"; break; in dump()
/freebsd/contrib/llvm-project/compiler-rt/lib/tsan/rtl/
H A Dtsan_interceptors_mac.cpp80 m(int32_t, int32_t, a32, f##32##Barrier, __tsan_atomic32_##tsan_atomic_f, \
84 m(int64_t, int64_t, a64, f##64##Barrier, __tsan_atomic64_##tsan_atomic_f, \
90 m(int32_t, uint32_t, a32, f##32##Barrier, __tsan_atomic32_##tsan_atomic_f, \
118 TSAN_INTERCEPTOR(bool, f##Barrier, t old_value, t new_value, \
120 SCOPED_TSAN_INTERCEPTOR(f##Barrier, old_value, new_value, ptr); \
148 OSATOMIC_INTERCEPTOR_BITOP(f##Barrier, op, clear, kMacOrderBarrier)
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUExportClustering.cpp76 DAG->addEdge(SUb, SDep(SUa, SDep::Barrier)); in buildCluster()
97 ToAdd.push_back(SDep(ExportPredSU, SDep::Barrier)); in removeExportDependencies()
H A DSIDefines.h1039 namespace Barrier {
/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h157 Barrier, enumerator
293 bool isBarrier() const { return Flags & (1ULL << MCID::Barrier); } in isBarrier()
/freebsd/contrib/llvm-project/openmp/runtime/src/
H A Dkmp_itt.inl409 does not have barrier object or barrier data structure. Barrier is just a
455 char const *type = "OMP Barrier";
472 type = "OMP For Barrier";
475 type = "OMP Sections Barrier";
478 type = "OMP Single Barrier";
481 type = "OMP Workshare Barrier";
484 type = "OMP Implicit Barrier";
489 type = "OMP Explicit Barrier";
506 type = "OMP Join Barrier";
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h69 Barrier, ///< An unknown scheduling barrier. enumerator
175 return getKind() == Order && Contents.OrdKind == Barrier; in isBarrier()
403 SDep Dep(SU, SDep::Barrier); in addPredBarrier()
H A DMachineInstr.h966 return hasProperty(MCID::Barrier, Type);
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGRecordLayoutBuilder.cpp537 bool Barrier = false; in accumulateBitFields() local
563 Barrier = true; in accumulateBitFields()
572 Barrier = true; in accumulateBitFields()
663 if (Barrier) in accumulateBitFields()
710 assert(!Barrier && "Accumulating across barrier"); in accumulateBitFields()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp329 DAG->addEdge(&DAG->SUnits[su], SDep(LastSequentialCall, SDep::Barrier)); in apply()
333 DAG->addEdge(&DAG->SUnits[su], SDep(&DAG->SUnits[su-1], SDep::Barrier)); in apply()
368 DAG->addEdge(&DAG->SUnits[su], SDep(LastVRegUse[*AI], SDep::Barrier)); in apply()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/IPO/
H A DOpenMPOpt.cpp4079 CallInst *Barrier = in insertInstructionGuardsHelper() local
4081 Barrier->setDebugLoc(DL); in insertInstructionGuardsHelper()
4082 OMPInfoCache.setCallingConvention(BarrierFn, Barrier); in insertInstructionGuardsHelper()
4086 CallInst *Barrier = in insertInstructionGuardsHelper() local
4089 Barrier->setDebugLoc(DL); in insertInstructionGuardsHelper()
4090 OMPInfoCache.setCallingConvention(BarrierFn, Barrier); in insertInstructionGuardsHelper()
4508 CallInst *Barrier = in buildCustomStateMachine() local
4510 OMPInfoCache.setCallingConvention(BarrierFn, Barrier); in buildCustomStateMachine()
4511 Barrier->setDebugLoc(DLoc); in buildCustomStateMachine()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/AsmParser/
H A DAArch64AsmParser.cpp509 struct BarrierOp Barrier; member
550 Barrier = o.Barrier; in AArch64Operand()
648 return Barrier.Val; in getBarrier()
653 return StringRef(Barrier.Data, Barrier.Length); in getBarrierName()
658 return Barrier.HasnXSModifier; in getBarriernXSModifier()
2418 Op->Barrier.Val = Val; in CreateBarrier()
2419 Op->Barrier.Data = Str.data(); in CreateBarrier()
2420 Op->Barrier.Length = Str.size(); in CreateBarrier()
2421 Op->Barrier.HasnXSModifier = HasnXSModifier; in CreateBarrier()
2458 Op->Barrier.Data = Str.data(); in CreatePrefetch()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.td43 def Barrier : BuiltinGroup;
626 // Barrier builtin records:
627 defm : DemangledNativeBuiltin<"barrier", OpenCL_std, Barrier, 1, 3, OpControlBarrier>;
628 defm : DemangledNativeBuiltin<"work_group_barrier", OpenCL_std, Barrier, 1, 3, OpControlBarrier>;
629 defm : DemangledNativeBuiltin<"__spirv_ControlBarrier", OpenCL_std, Barrier, 3, 3, OpControlBarrier…
H A DSPIRVBuiltins.cpp2432 case SPIRV::Barrier: in mapBuiltinToOpcode()
2535 case SPIRV::Barrier: in lowerBuiltin()
H A DSPIRVInstrInfo.td698 // 3.42.20 Barrier Instructions
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGFast.cpp326 SDep D(LoadSU, SDep::Barrier); in CopyAndMoveSuccessors()
H A DScheduleDAGSDNodes.cpp511 SDep Dep = isChain ? SDep(OpSU, SDep::Barrier) in AddSchedEdges()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrInfo.td1078 def SSNOP_MM : MMRel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM_MM<0x1>,
1080 def EHB_MM : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM_MM<0x3>,
1082 def PAUSE_MM : MMRel, Barrier<"pause", II_PAUSE>, BARRIER_FM_MM<0x5>,
H A DMicroMips32r6InstrInfo.td451 class EHB_MMR6_DESC : Barrier<"ehb", II_EHB>;
591 class PAUSE_MMR6_DESC : Barrier<"pause", II_PAUSE>;
605 class SSNOP_MMR6_DESC : Barrier<"ssnop", II_SSNOP>;
H A DMipsInstrInfo.td2441 class Barrier<string asmstr, InstrItinClass itin = NoItinerary> :
2444 def SSNOP : MMRel, StdMMR6Rel, Barrier<"ssnop", II_SSNOP>, BARRIER_FM<1>,
2446 def EHB : MMRel, Barrier<"ehb", II_EHB>, BARRIER_FM<3>, ISA_MIPS1;
2449 def PAUSE : MMRel, StdMMR6Rel, Barrier<"pause", II_PAUSE>, BARRIER_FM<5>,
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedCyclone.td290 // 7.8.14. Never-issued Instructions, Barrier and Hint Operations
H A DAArch64Features.td253 "Enable Armv8.5-A Speculation Barrier">;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMFeatures.td507 "Enable v8.5a Speculation Barrier" >;

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