| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | ISDOpcodes.h | 236 BUILD_PAIR, enumerator
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 657 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
665 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
680 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
722 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in ExpandADDSUB()
1678 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 1516 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in HexagonTargetLowering()
2930 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, Lo, Hi); in getCombine()
2938 DAG.getNode(ISD::BUILD_PAIR, dl, PairTy, in getCombine()
3485 if (Op0.getOpcode() == ISD::BUILD_PAIR) { in PerformDAGCombine()
3526 if (Op0.getOpcode() == ISD::BUILD_PAIR) { in PerformDAGCombine()
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| H A D | HexagonISelLoweringHVX.cpp | 1997 return DAG.getNode(ISD::BUILD_PAIR, dl, ResTy, Combines); in LowerHvxBitcast()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeTypesGeneric.cpp | 131 // Each iteration will BUILD_PAIR two nodes and append the result until in ExpandRes_BITCAST()
140 ISD::BUILD_PAIR, dl, in ExpandRes_BITCAST()
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| H A D | SelectionDAGDumper.cpp | 444 case ISD::BUILD_PAIR: return "build_pair"; in getOperationName()
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| H A D | LegalizeFloatTypes.cpp | 68 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
245 return DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), in SoftenFloatRes_BUILD_PAIR()
1396 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandFloatResult()
2008 Hi = DAG.getNode(ISD::BUILD_PAIR, dl, VT, Lo, Hi); in ExpandFloatRes_XINT_TO_FP()
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| H A D | LegalizeIntegerTypes.cpp | 66 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
1925 case ISD::BUILD_PAIR: Res = PromoteIntOp_BUILD_PAIR(N); break; in PromoteIntegerOperand()
2778 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandIntegerResult()
4629 Init = DAG.getNode(ISD::BUILD_PAIR, dl, StackSlotVT, AllZeros, Shiftee); in ExpandIntRes_ShiftThroughStack()
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| H A D | SelectionDAGBuilder.cpp | 215 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); in getCopyFromParts()
246 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); in getCopyFromParts()
5962 case ISD::BUILD_PAIR: in getUnderlyingArgRegs()
11747 if (!TM.Options.EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { in LowerArguments()
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| H A D | SelectionDAG.cpp | 1122 case ISD::BUILD_PAIR: { in VerifySDNode()
5284 case ISD::BUILD_PAIR: in canCreateUndefOrPoison()
7271 if (N1.getOpcode() == ISD::BUILD_PAIR) in getNode()
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| H A D | TargetLowering.cpp | 2401 case ISD::BUILD_PAIR: { in SimplifyDemandedBits()
7873 SDValue Dividend = DAG.getNode(ISD::BUILD_PAIR, dl, VT, LL, LH); in expandDIVREMByConstant()
7874 SDValue Rem = DAG.getNode(ISD::BUILD_PAIR, dl, VT, RemL, RemH); in expandDIVREMByConstant()
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| H A D | DAGCombiner.cpp | 1919 case ISD::BUILD_PAIR: return visitBUILD_PAIR(N); in visit()
15269 assert(N->getOpcode() == ISD::BUILD_PAIR); in CombineConsecutiveLoads()
15496 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); in visitBITCAST()
15565 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N0), VT, FlipBit, FlipBit); in visitBITCAST()
15584 if (N0.getOpcode() == ISD::BUILD_PAIR) in visitBITCAST()
15666 N0.getOpcode() == ISD::BUILD_PAIR || in visitFREEZE()
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| H A D | LegalizeDAG.cpp | 3998 case ISD::BUILD_PAIR: { in ExpandNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 294 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, Zero, SrcLo); in LowerShifts()
298 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, SrcHi, Zero); in LowerShifts()
318 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i32, Result.getValue(0), in LowerShifts()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 6189 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Read.getValue(0), in ExpandREAD_REGISTER()
6298 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Cvt, Cvt.getValue(1)); in ExpandBITCAST()
6753 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
6777 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in Expand64BitShift()
10125 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lower, Upper)); in ExpandDIV_Windows()
10181 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerLOAD()
10465 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Cycles32, in ReplaceREADCYCLECOUNTER()
10509 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i64, Lo, Hi)); in ReplaceCMP_SWAP_64Results()
10719 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, in ReplaceLongIntrinsic()
13737 if (NB->getOpcode() != ISD::BUILD_PAIR) in PerformADDVecReduce()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 491 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
547 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments_32()
3624 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops); in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 1253 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in lowerBITCAST()
1293 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); in extractLOHI()
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| H A D | MipsISelLowering.cpp | 1066 CurDAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, ResLo, ResHi); in performMADD_MSUBCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 747 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in PPCTargetLowering()
6645 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in LowerCall_64SVR4()
9341 if (!Subtarget.isPPC64() || (Op0.getOpcode() != ISD::BUILD_PAIR) || in LowerBITCAST()
11905 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, RTB, RTB.getValue(1))); in ReplaceNodeResults()
11928 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128, in ReplaceNodeResults()
16384 Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Hi, Lo); in PerformDAGCombine()
16386 Res = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in PerformDAGCombine()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 348 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in WebAssemblyTargetLowering()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelDAGToDAG.cpp | 569 case ISD::BUILD_PAIR: { in Select()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 12316 DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, RCW, RCW.getValue(1))); in ReplaceNodeResults()
12358 return DAG.getNode(ISD::BUILD_PAIR, DL, N->getValueType(0), Lo, Hi); in ReplaceNodeResults()
12625 SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, in ReplaceNodeResults()
12714 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi)); in ReplaceNodeResults()
12874 DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, EltLo, EltHi)); in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 526 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand); in AArch64TargetLowering()
26011 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Lo, Hi)); in ReplaceCMP_SWAP_128Results()
26045 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128, in ReplaceCMP_SWAP_128Results()
26178 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, Lo, Hi)); in ReplaceATOMIC_LOAD_128Results()
26309 DAG.getNode(ISD::BUILD_PAIR, SDLoc(N), MVT::i128, in ReplaceNodeResults()
26399 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128, in ReplaceNodeResults()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZISelLowering.cpp | 1573 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128, Lo, Hi); in lowerGR128ToI128()
6289 return DAG.getNode(ISD::BUILD_PAIR, SL, MVT::i128, Lo, Hi); in expandBitCastF128ToI128()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 6350 SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i128, in ReplaceCopyFromReg_128()
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