Searched refs:BIT_1 (Results 1 – 6 of 6) sorted by relevance
190 #define BIT_1 (1 << 1) macro339 #define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */372 #define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */389 #define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */402 #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */802 #define CS_RST_CLR BIT_1 /* Clear Software Reset */805 #define LED_STAT_ON BIT_1 /* Status LED On */815 #define PC_VCC_ON BIT_1 /* Switch VCC On */845 #define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */878 #define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */[all …]
40 #define BIT_1 (0x1 << 1) macro188 #define Q81_CTL_SYSTEM_ENABLE_FAE BIT_1258 #define Q81_CTL_CONFIG_DRQ BIT_1275 #define Q81_CTL_STATUS_PI BIT_1300 #define Q81_CTL_INTRM_HL0 BIT_1471 #define Q81_CTL_RD_MCAST BIT_1616 #define Q81_RXB_DESC_BADDR_LO_S BIT_1653 #define Q81_TX_MAC_FLAGS_I BIT_1659 #define Q81_TX_MAC_VLAN_OFF_DFP BIT_1687 #define Q81_TX_TSO_FLAGS_I BIT_1[all …]
39 #define BIT_1 (0x1 << 1) macro
327 while (!((val = READ_OFFSET32(ha, Q8_ROM_STATUS)) & BIT_1)) { in qla_rd_flash32()659 if (val & BIT_1) in qla_wait_for_flash_busy()
119 data = BIT_1; in ql_rdwr_offchip_mem()150 data = (BIT_2|BIT_1|BIT_0); in ql_rdwr_offchip_mem()156 data = (BIT_1|BIT_0); in ql_rdwr_offchip_mem()