Lines Matching refs:BIT_1
190 #define BIT_1 (1 << 1) macro
339 #define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
372 #define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
389 #define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */
402 #define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */
802 #define CS_RST_CLR BIT_1 /* Clear Software Reset */
805 #define LED_STAT_ON BIT_1 /* Status LED On */
815 #define PC_VCC_ON BIT_1 /* Switch VCC On */
845 #define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */
878 #define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */
892 #define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */
939 #define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */
944 #define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */
962 #define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */
968 #define TIM_STOP BIT_1 /* Stop Timer */
975 #define TIM_T_OFF BIT_1 /* Test mode off */
983 #define DPT_START BIT_1 /* Start Descriptor Poll Timer */
993 #define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */
1029 #define I2C_DATA BIT_1 /* I2C Data Port */
1037 #define BSC_START BIT_1 /* Start Blink Source Counter */
1045 #define BSC_T_OFF BIT_1 /* Test mode off */
1059 #define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */
1078 #define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */
1086 #define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */
1114 #define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */
1144 #define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */
1163 #define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */
1171 #define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */
1179 #define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */
1236 #define WOL_CTL_ENA_PATTERN_UNIT BIT_1
1387 #define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */
1435 #define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */
1459 #define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */
1481 #define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */
1511 #define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */
1612 #define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */
1838 #define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */
1920 #define GMR_FS_CRC_ERR BIT_1 /* CRC Error */
1979 #define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
2006 #define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */
2014 #define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */
2022 #define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */
2047 #define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1
2052 #define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */
2059 #define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */
2077 #define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
2102 #define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */
2111 #define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */
2117 #define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */