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Searched refs:BITREVERSE (Results 1 – 25 of 29) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp3532 { ISD::BITREVERSE, MVT::v2i64, { 3, 10, 10, 11 } }, in getIntrinsicInstrCost()
3533 { ISD::BITREVERSE, MVT::v4i64, { 3, 11, 10, 11 } }, in getIntrinsicInstrCost()
3534 { ISD::BITREVERSE, MVT::v8i64, { 3, 12, 10, 14 } }, in getIntrinsicInstrCost()
3535 { ISD::BITREVERSE, MVT::v4i32, { 3, 10, 10, 11 } }, in getIntrinsicInstrCost()
3536 { ISD::BITREVERSE, MVT::v8i32, { 3, 11, 10, 11 } }, in getIntrinsicInstrCost()
3537 { ISD::BITREVERSE, MVT::v16i32, { 3, 12, 10, 14 } }, in getIntrinsicInstrCost()
3538 { ISD::BITREVERSE, MVT::v8i16, { 3, 10, 10, 11 } }, in getIntrinsicInstrCost()
3539 { ISD::BITREVERSE, MVT::v16i16, { 3, 11, 10, 11 } }, in getIntrinsicInstrCost()
3540 { ISD::BITREVERSE, MVT::v32i16, { 3, 12, 10, 14 } }, in getIntrinsicInstrCost()
3541 { ISD::BITREVERSE, MVT::v16i8, { 2, 5, 9, 9 } }, in getIntrinsicInstrCost()
[all …]
H A DX86ISelLowering.cpp1306 setOperationAction(ISD::BITREVERSE, MVT::i8, Custom); in X86TargetLowering()
1307 setOperationAction(ISD::BITREVERSE, MVT::i16, Custom); in X86TargetLowering()
1308 setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); in X86TargetLowering()
1309 setOperationAction(ISD::BITREVERSE, MVT::i64, Custom); in X86TargetLowering()
1318 setOperationAction(ISD::BITREVERSE, VT, Custom); in X86TargetLowering()
1410 setOperationAction(ISD::BITREVERSE, VT, Custom); in X86TargetLowering()
1534 setOperationAction(ISD::BITREVERSE, VT, Custom); in X86TargetLowering()
1930 setOperationAction(ISD::BITREVERSE, VT, Custom); in X86TargetLowering()
2526 ISD::BITREVERSE, in X86TargetLowering()
29085 case ISD::BITREVERSE: in getGFNICtrlImm()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h746 BITREVERSE, enumerator
H A DSDPatternMatch.h680 return UnaryOpc_match<Opnd>(ISD::BITREVERSE, Op);
H A DBasicTTIImpl.h2327 ISD = ISD::BITREVERSE; in getTypeBasedIntrinsicInstrCost()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeVectorOps.cpp377 case ISD::BITREVERSE: in LegalizeOp()
943 case ISD::BITREVERSE: in Expand()
1365 if (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, VT.getScalarType())) { in ExpandBITREVERSE()
1381 (TLI.isOperationLegalOrCustom(ISD::BITREVERSE, ByteVT) || in ExpandBITREVERSE()
1390 Op = DAG.getNode(ISD::BITREVERSE, DL, ByteVT, Op); in ExpandBITREVERSE()
H A DSelectionDAGDumper.cpp483 case ISD::BITREVERSE: return "bitreverse"; in getOperationName()
H A DLegalizeIntegerTypes.cpp63 case ISD::BITREVERSE: Res = PromoteIntRes_BITREVERSE(N); break; in PromoteIntegerResult()
609 !TLI.isOperationLegalOrCustomOrPromote(ISD::BITREVERSE, NVT)) { in PromoteIntRes_BITREVERSE()
616 if (N->getOpcode() == ISD::BITREVERSE) in PromoteIntRes_BITREVERSE()
618 DAG.getNode(ISD::BITREVERSE, dl, NVT, Op), ShAmt); in PromoteIntRes_BITREVERSE()
2786 case ISD::BITREVERSE: ExpandIntRes_BITREVERSE(N, Lo, Hi); break; in ExpandIntegerResult()
3745 Lo = DAG.getNode(ISD::BITREVERSE, dl, Lo.getValueType(), Lo); in ExpandIntRes_BITREVERSE()
3746 Hi = DAG.getNode(ISD::BITREVERSE, dl, Hi.getValueType(), Hi); in ExpandIntRes_BITREVERSE()
H A DSelectionDAG.cpp4050 case ISD::BITREVERSE: { in computeKnownBits()
5275 case ISD::BITREVERSE: in canCreateUndefOrPoison()
5598 case ISD::BITREVERSE: in isKnownNeverZero()
5936 case ISD::BITREVERSE: in getNode()
6144 case ISD::BITREVERSE: in getNode()
6423 case ISD::BITREVERSE: in FoldConstantArithmetic()
H A DLegalizeVectorTypes.cpp84 case ISD::BITREVERSE: in ScalarizeVectorResult()
1151 case ISD::BITREVERSE: in SplitVectorResult()
4562 case ISD::BITREVERSE: in WidenVectorResult()
H A DLegalizeDAG.cpp3091 case ISD::BITREVERSE: in ExpandNode()
5167 case ISD::BITREVERSE: in PromoteNode()
H A DDAGCombiner.cpp1896 case ISD::BITREVERSE: return visitBITREVERSE(N); in visit()
10287 if (Opcode != ISD::BSWAP && Opcode != ISD::BITREVERSE) in foldBitOrderCrossLogicOp()
11042 if (N0.getOpcode() == ISD::BITREVERSE && N0.hasOneUse()) { in visitBSWAP()
11044 return DAG.getNode(ISD::BITREVERSE, DL, VT, BSwap); in visitBSWAP()
11095 if (SDValue C = DAG.FoldConstantArithmetic(ISD::BITREVERSE, DL, VT, {N0})) in visitBITREVERSE()
11099 if (N0.getOpcode() == ISD::BITREVERSE) in visitBITREVERSE()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp56 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in CSKYTargetLowering()
104 setOperationAction(ISD::BITREVERSE, MVT::i32, Expand); in CSKYTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1589 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in HexagonTargetLowering()
1590 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in HexagonTargetLowering()
1651 ISD::CTPOP, ISD::CTLZ, ISD::CTTZ, ISD::BSWAP, ISD::BITREVERSE, in HexagonTargetLowering()
1727 setOperationAction(ISD::BITREVERSE, NativeVT, Legal); in HexagonTargetLowering()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DVPIntrinsics.def256 VP_PROPERTY_FUNCTIONAL_SDOPC(BITREVERSE)
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp104 setOperationAction(ISD::BITREVERSE, MVT::i8, Custom); in LoongArchTargetLowering()
105 setOperationAction(ISD::BITREVERSE, GRLenVT, Legal); in LoongArchTargetLowering()
142 setOperationAction(ISD::BITREVERSE, MVT::i32, Custom); in LoongArchTargetLowering()
2909 case ISD::BITREVERSE: { in ReplaceNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp491 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in AArch64TargetLowering()
492 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in AArch64TargetLowering()
1251 setOperationAction(ISD::BITREVERSE, MVT::v8i8, Legal); in AArch64TargetLowering()
1252 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Legal); in AArch64TargetLowering()
1253 setOperationAction(ISD::BITREVERSE, MVT::v2i32, Custom); in AArch64TargetLowering()
1254 setOperationAction(ISD::BITREVERSE, MVT::v4i32, Custom); in AArch64TargetLowering()
1255 setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom); in AArch64TargetLowering()
1256 setOperationAction(ISD::BITREVERSE, MVT::v2i64, Custom); in AArch64TargetLowering()
1431 setOperationAction(ISD::BITREVERSE, VT, Custom); in AArch64TargetLowering()
1710 setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom); in AArch64TargetLowering()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp370 setOperationAction(ISD::BITREVERSE, XLenVT, Legal); in RISCVTargetLowering()
373 setOperationAction(ISD::BITREVERSE, XLenVT, in RISCVTargetLowering()
908 setOperationAction(ISD::BITREVERSE, VT, Legal); in RISCVTargetLowering()
914 setOperationAction({ISD::BITREVERSE, ISD::VP_BITREVERSE}, VT, Expand); in RISCVTargetLowering()
1271 setOperationAction({ISD::BITREVERSE, ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF, in RISCVTargetLowering()
1487 setTargetDAGCombine(ISD::BITREVERSE); in RISCVTargetLowering()
4916 if (!Subtarget.getTargetLowering()->isOperationLegalOrCustom(ISD::BITREVERSE, in lowerBitreverseShuffle()
4929 DAG.getNode(ISD::BITREVERSE, DL, ViaVT, DAG.getBitcast(ViaVT, V)); in lowerBitreverseShuffle()
5974 OP_CASE(BITREVERSE) in getRISCVVLOp()
6021 VP_CASE(BITREVERSE) // VP_BITREVERS in getRISCVVLOp()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp760 setOperationAction({ISD::BITREVERSE, ISD::PARITY}, VT, Expand); in initActions()
H A DCodeGenPrepare.cpp8483 !TLI->isOperationLegalOrCustom(ISD::BITREVERSE, in makeBitReverse()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp530 ISD::BITREVERSE, ISD::CTLZ, ISD::CTPOP, ISD::CTTZ, in NVPTXTargetLowering()
570 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in NVPTXTargetLowering()
571 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in NVPTXTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp108 setOperationAction(ISD::BITREVERSE , MVT::i32, Legal); in XCoreTargetLowering()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp194 setOperationAction(ISD::BITREVERSE, IntVT, Act); in initSPUActions()
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSelectionDAG.td473 def bitreverse : SDNode<"ISD::BITREVERSE" , SDTIntUnaryOp>;
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp280 setOperationAction(ISD::BITREVERSE, VT, Legal); in addMVEVectorTypes()
1198 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in ARMTargetLowering()
6570 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, VT, N->getOperand(0)); in LowerCTTZ()
8638 SDValue rbit = DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, cast); in LowerVECTOR_SHUFFLE_i1()
10157 DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, Load), in LowerPredicateLoad()
10216 DAG.getNode(ISD::BITREVERSE, dl, MVT::i32, GRP), in LowerPredicateStore()

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