Lines Matching refs:BITREVERSE
491 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal); in AArch64TargetLowering()
492 setOperationAction(ISD::BITREVERSE, MVT::i64, Legal); in AArch64TargetLowering()
1251 setOperationAction(ISD::BITREVERSE, MVT::v8i8, Legal); in AArch64TargetLowering()
1252 setOperationAction(ISD::BITREVERSE, MVT::v16i8, Legal); in AArch64TargetLowering()
1253 setOperationAction(ISD::BITREVERSE, MVT::v2i32, Custom); in AArch64TargetLowering()
1254 setOperationAction(ISD::BITREVERSE, MVT::v4i32, Custom); in AArch64TargetLowering()
1255 setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom); in AArch64TargetLowering()
1256 setOperationAction(ISD::BITREVERSE, MVT::v2i64, Custom); in AArch64TargetLowering()
1431 setOperationAction(ISD::BITREVERSE, VT, Custom); in AArch64TargetLowering()
1710 setOperationAction(ISD::BITREVERSE, MVT::v1i64, Custom); in AArch64TargetLowering()
1734 setOperationAction(ISD::BITREVERSE, VT, Custom); in AArch64TargetLowering()
2041 setOperationAction(ISD::BITREVERSE, VT, Default); in addTypeForFixedLengthSVE()
7024 case ISD::BITREVERSE: in LowerOperation()
10144 SDValue RBIT = DAG.getNode(ISD::BITREVERSE, DL, VT, Op.getOperand(0)); in LowerCTTZ()
10242 DAG.getNode(ISD::BITREVERSE, DL, VST, REVB)); in LowerBitreverse()
24447 if (!Subtarget->hasCSSC() || BR.getOpcode() != ISD::BITREVERSE || in performCTLZCombine()