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Searched refs:BF16 (Results 1 – 25 of 26) sorted by relevance

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/freebsd/contrib/llvm-project/clang/include/clang/Basic/
H A Darm_bf16.td1 //===--- arm_bf16.td - ARM BF16 compiler interface ------------------------===//
9 // This file defines the TableGen definitions from which the ARM BF16 header
H A Driscv_vector.td1764 // Vector BF16 widening multiply-accumulate
1778 // Vector BF16 widening multiply-accumulate
1933 // Zvfbfmin - Vector convert BF16 to FP32
2025 // Zvfbfmin - Vector convert FP32 to BF16
2075 // Zvfbfmin - Vector convert FP32 to BF16
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.td1118 int BF16 = 2;
1135 def SSrc_bf16: SrcRegOrImm9 <SReg_32, "OPW32", "OPERAND_REG_IMM_BF16", 16, OperandSemantics.BF16>;
1170 def VSrc_bf16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_BF16", 16, OperandSemantics.BF16>;
1204 …f16_Lo128 : SrcRegOrImm9 <VS_32_Lo128, "OPW16", "OPERAND_REG_IMM_BF16", 16, OperandSemantics.BF16>;
1210 def VSrc_v2bf16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_IMM_V2BF16", 16, OperandSemantics.BF16…
1224 …: SrcRegOrImmDeferred9<VS_32, "OPW16", "OPERAND_REG_IMM_BF16_DEFERRED", 16, OperandSemantics.BF16>;
1229 …egOrImmDeferred9<VS_32_Lo128, "OPW16", "OPERAND_REG_IMM_BF16_DEFERRED", 16, OperandSemantics.BF16>;
1294 …VCSrc_bf16 : SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_BF16", 16, OperandSemantics.BF16>;
1299 …rc_v2bf16: SrcRegOrImm9 <VS_32, "OPW32", "OPERAND_REG_INLINE_C_V2BF16", 16, OperandSemantics.BF16>;
1306 …_64_bf16 : SrcRegOrImm9 <VReg_64, "OPW64", "OPERAND_REG_INLINE_C_BF16", 16, OperandSemantics.BF16>;
[all …]
H A DSIDefines.h277 BF16 = 2, enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp77 MCInstBuilder(MI.getOpcode() == CSKY::JBT_E ? CSKY::BF16 : CSKY::BT16) in expandJBTF()
186 TmpInst = MCInstBuilder(CSKY::BF16) in encodeInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td210 def BF16 : J16_B<3, "bf16">;
493 (BF16 (inst mGPR:$rs1, imm_ty:$rs2), bb:$offset)>;
503 (BF16 (CMPNE16 sGPR:$rs1, sGPR:$rs2), bb:$offset)>;
514 defm : BTF16Pat1<setult, setugt, CMPHS16, BF16>;
516 defm : BTF16Pat1<setge, setle, CMPLT16, BF16>;
H A DCSKYInstrInfo.cpp197 return CSKY::BF16; in getOppositeBranchOpc()
200 case CSKY::BF16: in getOppositeBranchOpc()
H A DCSKYConstantIslandPass.cpp511 case CSKY::BF16: in initializeFunctionInfo()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVFeatures.td321 : RISCVExtension<"zfbfmin", 1, 0, "'Zfbfmin' (Scalar BF16 Converts)",
325 "'Zfbfmin' (Scalar BF16 Converts)">;
333 "'Zfbfmin' (Scalar BF16 Converts)">;
698 : RISCVExtension<"zvfbfmin", 1, 0, "'Zvbfmin' (Vector BF16 Converts)",
702 "'Zvfbfmin' (Vector BF16 Converts)">;
706 "'Zvfbfwma' (Vector BF16 widening mul-add)",
710 "'Zvfbfwma' (Vector BF16 widening mul-add)">;
H A DRISCVInstrInfoVPseudos.td206 // BF16 uses the same register class as F16.
/freebsd/sys/arm64/arm64/
H A Didentcpu.c855 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ISAR1, BF16, NONE, IMPL),
997 MRS_FIELD_HWCAP(ID_AA64ISAR1, BF16, false, MRS_LOWER, MRS_USERSPACE,
1910 MRS_FIELD_VALUE_NONE_IMPL(ID_AA64ZFR0, BF16, NONE, BASE),
1967 MRS_FIELD_HWCAP(ID_AA64ZFR0, BF16, false, MRS_LOWER, MRS_USERSPACE,
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/Disassembler/
H A DCSKYDisassembler.cpp436 case CSKY::BF16: in handleCROperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedNeoverseN2.td1148 // ASIMD BFloat16 (BF16) instructions
1151 // ASIMD convert, F32 to BF16
1164 // Scalar convert, F32 to BF16
2070 // SVE BFloat16 (BF16) instructions
2073 // Convert, F32 to BF16
H A DAArch64SchedNeoverseV1.td975 // ASIMD convert, F32 to BF16
987 // Scalar convert, F32 to BF16
1677 // SVE BFloat16 (BF16) instructions
1680 // Convert, F32 to BF16
H A DAArch64SchedNeoverseV2.td1650 // ASIMD BFloat16 (BF16) instructions
1653 // ASIMD convert, F32 to BF16
1666 // Scalar convert, F32 to BF16
2590 // SVE BFloat16 (BF16) instructions
2593 // Convert, F32 to BF16
H A DAArch64SchedA510.td1153 // SVE BFloat16 (BF16) instructions
1156 // Convert, F32 to BF16
H A DAArch64Features.td281 def FeatureBF16 : ExtensionWithMArch<"bf16", "BF16", "FEAT_BF16",
H A DAArch64InstrInfo.td1398 // Round FP32 to BF16.
4896 // Pattern for FP16 and BF16 immediates
6057 // Round FP64 to BF16.
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1388 return (Sema == AMDGPU::OperandSemantics::BF16) ? getInlineImmValBF16(Imm) in getInlineImmVal16()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86.td265 "Support AMX-BF16 instructions",
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.td1363 bit IsBfloat16 = !or(!not(!eq(!find(name, "BF16"), -1)),
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXInstrInfo.td1208 // BF16 NEG
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstrNEON.td6492 // If VMOVH (vmovx.f16) is available use it to extract BF16 from the odd lanes
/freebsd/crypto/heimdal/lib/wind/
H A DNormalizationTest.txt7207 BF16;BF16;1108 1167 11B5;BF16;1108 1167 11B5; # (뼖; 뼖; 뼖; 뼖; 뼖; ) HANGUL SYLLABLE BBYEOLP
/freebsd/tools/tools/locale/etc/final-maps/
H A Dwidths.txt102729 <CJK_UNIFIED_IDEOGRAPH-2BF16> 2

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