Searched refs:AssignedReg (Results 1 – 6 of 6) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 94 Register AssignedReg; in getRegistersForValue() local
96 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( in getRegistersForValue()
122 if (AssignedReg) { in getRegistersForValue()
123 for (; *I != AssignedReg; ++I) in getRegistersForValue()
131 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); in getRegistersForValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 605 Register AssignedReg = FuncInfo.ValueMap[I]; in SelectLoad() local
607 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in SelectLoad()
1173 Register AssignedReg = FuncInfo.ValueMap[I]; in PPCMoveToIntReg() local
1175 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr; in PPCMoveToIntReg()
1279 Register AssignedReg = FuncInfo.ValueMap[I]; in SelectBinaryIntOp() local
1281 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectBinaryIntOp()
1922 Register AssignedReg = FuncInfo.ValueMap[I]; in SelectIntExt() local
1924 (AssignedReg ? MRI.getRegClass(AssignedReg) : in SelectIntExt()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocFast.cpp | 384 MCPhysReg AssignedReg, bool Kill, bool LiveOut);
565 Register VirtReg, MCPhysReg AssignedReg, bool Kill, in spill() argument
568 << printReg(AssignedReg, TRI)); in spill()
573 TII->storeRegToStackSlot(*MBB, Before, AssignedReg, Kill, FI, &RC, TRI, in spill()
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| H A D | RegAllocGreedy.cpp | 1853 MCRegister AssignedReg = VRM.getPhys(Intf.reg()); in assignedRegPartiallyOverlaps() local
1854 if (PhysReg == AssignedReg) in assignedRegPartiallyOverlaps()
1856 return TRI.regsOverlap(PhysReg, AssignedReg); in assignedRegPartiallyOverlaps()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 368 Register &AssignedReg = FuncInfo.ValueMap[I]; in updateValueMap() local
369 if (!AssignedReg) in updateValueMap()
371 AssignedReg = Reg; in updateValueMap()
372 else if (Reg != AssignedReg) { in updateValueMap()
375 FuncInfo.RegFixups[AssignedReg + i] = Reg + i; in updateValueMap()
379 AssignedReg = Reg; in updateValueMap()
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| H A D | SelectionDAGBuilder.cpp | 9615 unsigned AssignedReg; in getRegistersForValue() local
9617 std::tie(AssignedReg, RC) = TLI.getRegForInlineAsmConstraint( in getRegistersForValue()
9688 if (AssignedReg) { in getRegistersForValue()
9689 I = std::find(I, RC->end(), AssignedReg); in getRegistersForValue()
9693 return {AssignedReg}; in getRegistersForValue()
9699 Register R = AssignedReg ? Register(*I) : RegInfo.createVirtualRegister(RC); in getRegistersForValue()
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