| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCCallingConv.cpp | 71 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local
75 const unsigned NumArgRegs = std::size(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
77 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
84 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
96 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128() local
100 const unsigned NumArgRegs = std::size(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
102 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
109 State.AllocateReg(ArgRegs[RegNum + i]); in CC_PPC32_SVR4_Custom_SkipLastArgRegsPPCF128()
121 static const MCPhysReg ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
126 const unsigned NumArgRegs = std::size(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
[all …]
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| H A D | PPCFastISel.cpp | 174 SmallVectorImpl<Register> &ArgRegs,
1364 SmallVectorImpl<Register> &ArgRegs, in processCallArgs() argument
1418 Register Arg = ArgRegs[VA.getValNo()]; in processCallArgs()
1589 SmallVector<Register, 8> ArgRegs; in fastLowerCall() local
1594 ArgRegs.reserve(NumArgs); in fastLowerCall()
1623 ArgRegs.push_back(Arg); in fastLowerCall()
1632 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in fastLowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsCallLowering.cpp | 406 ArrayRef<MCPhysReg> ArgRegs = in lowerFormalArguments() local
408 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in lowerFormalArguments()
412 if (ArgRegs.size() == Idx) in lowerFormalArguments()
417 (int)(RegSize * (ArgRegs.size() - Idx)); in lowerFormalArguments()
424 for (unsigned I = Idx; I < ArgRegs.size(); ++I, VaArgOffset += RegSize) { in lowerFormalArguments()
425 MIRBuilder.getMBB().addLiveIn(ArgRegs[I]); in lowerFormalArguments()
428 MIRBuilder.buildCopy(RegTy, Register(ArgRegs[I])); in lowerFormalArguments()
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| H A D | MipsISelLowering.cpp | 4607 ArrayRef<MCPhysReg> ArgRegs = ABI.GetByValArgRegs(); in passByValArg() local
4618 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4667 unsigned ArgReg = ArgRegs[FirstReg + I]; in passByValArg()
4690 ArrayRef<MCPhysReg> ArgRegs = ABI.getVarArgRegs(Subtarget.isGP64bit()); in writeVarArgRegs() local
4691 unsigned Idx = State.getFirstUnallocated(ArgRegs); in writeVarArgRegs()
4702 if (ArgRegs.size() == Idx) in writeVarArgRegs()
4707 (int)(RegSizeInBytes * (ArgRegs.size() - Idx)); in writeVarArgRegs()
4719 for (unsigned I = Idx; I < ArgRegs.size(); in writeVarArgRegs()
4721 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 471 ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI()); in saveVarArgRegisters() local
473 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in saveVarArgRegisters()
479 int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in saveVarArgRegisters()
511 for (unsigned I = Idx; I < ArgRegs.size(); ++I) { in saveVarArgRegisters()
514 VReg, ArgRegs[I], in saveVarArgRegisters()
516 ArgRegs[I], XLenVT, CCValAssign::Full)); in saveVarArgRegisters()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/ |
| H A D | SPIRVCallLowering.h | 34 SmallVector<Register> ArgRegs; member
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| H A D | SPIRVCallLowering.cpp | 531 if (!GR->getSPIRVTypeForVReg(IC.ArgRegs[i])) in produceIndirectPtrTypes()
532 GR->assignSPIRVTypeToVReg(SPIRVTy, IC.ArgRegs[i], MF); in produceIndirectPtrTypes()
700 IndirectCall.ArgRegs.push_back(Arg.Regs[0]); in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 542 static const MCPhysReg ArgRegs[] = {ARC::R0, ARC::R1, ARC::R2, ARC::R3, in LowerCallArguments() local
545 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCallArguments()
546 if (FirstVAReg < std::size(ArgRegs)) { in LowerCallArguments()
552 int VarFI = MFI.CreateFixedObject((std::size(ArgRegs) - FirstVAReg) * 4, in LowerCallArguments()
556 for (unsigned i = FirstVAReg; i < std::size(ArgRegs); i++) { in LowerCallArguments()
559 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCallArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUCallLowering.h | 56 SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs,
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| H A D | AMDGPUCallLowering.cpp | 754 … SmallVectorImpl<std::pair<MCRegister, Register>> &ArgRegs, in passSpecialInputs() argument
843 ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
942 ArgRegs.emplace_back(OutgoingArg->getRegister(), InputReg); in passSpecialInputs()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMFastISel.cpp | 242 SmallVectorImpl<Register> &ArgRegs,
1938 SmallVectorImpl<Register> &ArgRegs, in ProcessCallArgs() argument
2005 Register Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
2288 SmallVector<Register, 8> ArgRegs; in ARMEmitLibcall() local
2292 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall()
2308 ArgRegs.push_back(Arg); in ARMEmitLibcall()
2316 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall()
2399 SmallVector<Register, 8> ArgRegs; in SelectCall() local
2404 ArgRegs.reserve(arg_size); in SelectCall()
2442 ArgRegs.push_back(Arg); in SelectCall()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 371 ArrayRef<MCPhysReg> ArgRegs = ArrayRef(GPRArgRegs); in LowerFormalArguments() local
372 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
385 if (ArgRegs.size() == Idx) { in LowerFormalArguments()
389 VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments()
400 for (unsigned I = Idx; I < ArgRegs.size(); in LowerFormalArguments()
403 RegInfo.addLiveIn(ArgRegs[I], Reg); in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 1222 static const MCPhysReg ArgRegs[] = { in LowerCCCArguments() local
1226 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs); in LowerCCCArguments()
1227 if (FirstVAReg < std::size(ArgRegs)) { in LowerCCCArguments()
1231 for (int i = std::size(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments()
1241 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | CallLowering.h | 599 ArrayRef<ArrayRef<Register>> ArgRegs, Register SwiftErrorVReg,
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 95 ArrayRef<ArrayRef<Register>> ArgRegs, in lowerCall() argument
135 ArgInfo OrigArg{ArgRegs[i], *Arg.get(), i, getAttributesForArgIdx(CB, i), in lowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 588 static const MCPhysReg ArgRegs[] = { in LowerFormalArguments_32() local
591 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments_32()
592 const MCPhysReg *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments_32()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 141 static const MCPhysReg ArgRegs[] = { in CC_SkipOdd() local
145 const unsigned NumArgRegs = std::size(ArgRegs); in CC_SkipOdd()
146 unsigned RegNum = State.getFirstUnallocated(ArgRegs); in CC_SkipOdd()
150 State.AllocateReg(ArgRegs[RegNum]); in CC_SkipOdd()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 3326 SmallVector<Register, 16> ArgRegs; in fastLowerCall() local
3370 ArgRegs.push_back(ResultReg); in fastLowerCall()
3401 Register ArgReg = ArgRegs[VA.getValNo()]; in fastLowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 7153 ArrayRef<MCPhysReg> ArgRegs = ArrayRef(ArgGPRs); in LowerFormalArguments() local
7154 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
7167 if (ArgRegs.size() == Idx) { in LowerFormalArguments()
7171 VarArgsSaveSize = GRLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments()
7191 for (unsigned I = Idx; I < ArgRegs.size(); in LowerFormalArguments()
7194 RegInfo.addLiveIn(ArgRegs[I], Reg); in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 22363 ArrayRef<MCPhysReg> ArgRegs = RISCV::getArgGPRs(Subtarget.getTargetABI()); in LowerFormalArguments() local
22364 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs); in LowerFormalArguments()
22372 int VarArgsSaveSize = XLenInBytes * (ArgRegs.size() - Idx); in LowerFormalArguments()
22397 for (unsigned I = Idx; I < ArgRegs.size(); ++I) { in LowerFormalArguments()
22399 RegInfo.addLiveIn(ArgRegs[I], Reg); in LowerFormalArguments()
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