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Searched refs:AndMask (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp238 const APInt &AndMask = N->getConstantOperandAPInt(1); in selectShiftMask() local
243 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
245 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask()
253 if (ShMask.isSubsetOf(AndMask | Known.Zero)) { in selectShiftMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp1578 static void printSwizzleBitmask(const uint16_t AndMask, in printSwizzleBitmask() argument
1584 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask; in printSwizzleBitmask()
1585 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask; in printSwizzleBitmask()
1635 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK; in printSwizzle() local
1639 if (AndMask == BITMASK_MAX && OrMask == 0 && llvm::popcount(XorMask) == 1) { in printSwizzle()
1646 } else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 && in printSwizzle()
1656 uint16_t GroupSize = BITMASK_MAX - AndMask + 1; in printSwizzle()
1672 printSwizzleBitmask(AndMask, OrMask, XorMask, O); in printSwizzle()
/freebsd/lib/libvgl/
H A Dvgl.h128 void VGLMouseSetImage(VGLBitmap *AndMask, VGLBitmap *OrMask);
H A Dmouse.c252 VGLMouseSetImage(VGLBitmap *AndMask, VGLBitmap *OrMask) in VGLMouseSetImage() argument
258 VGLMouseAndMask = AndMask; in VGLMouseSetImage()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp178 APInt AndMask; in selectShiftMask() local
194 if (mi_match(ShAmtReg, MRI, m_GAnd(m_Reg(AndSrcReg), m_ICst(AndMask)))) { in selectShiftMask()
195 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
196 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask()
202 if (ShMask.isSubsetOf(AndMask | Known.Zero)) in selectShiftMask()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp135 APInt AndMask; in foldSelectICmpAnd() local
147 AndMask = *AndRHS; in foldSelectICmpAnd()
149 Pred, V, AndMask)) { in foldSelectICmpAnd()
151 if (!AndMask.isPowerOf2()) in foldSelectICmpAnd()
169 if (TC.getBitWidth() != AndMask.getBitWidth() || (TC ^ FC) != AndMask) in foldSelectICmpAnd()
176 V = Builder.CreateAnd(V, ConstantInt::get(SelType, AndMask)); in foldSelectICmpAnd()
204 unsigned AndZeros = AndMask.logBase2(); in foldSelectICmpAnd()
216 V = Builder.CreateAnd(V, ConstantInt::get(V->getType(), AndMask)); in foldSelectICmpAnd()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp760 uint64_t AndMask = MaskNode->getZExtValue(); in detectOrAndInsertion() local
761 if (InsertMask & AndMask) in detectOrAndInsertion()
767 if (Used != (AndMask | InsertMask)) { in detectOrAndInsertion()
769 if (Used != (AndMask | InsertMask | Known.Zero.getZExtValue())) in detectOrAndInsertion()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DDataFlowSanitizer.cpp282 uint64_t AndMask; member
1907 uint64_t AndMask = MapParams->AndMask; in getShadowOffset() local
1908 if (AndMask) in getShadowOffset()
1910 IRB.CreateAnd(OffsetLong, ConstantInt::get(IntptrTy, ~AndMask)); in getShadowOffset()
H A DMemorySanitizer.cpp384 uint64_t AndMask; member
978 CustomMapParams.AndMask = ClAndMask; in initializeModule()
1713 if (uint64_t AndMask = MS.MapParams->AndMask) in getShadowPtrOffset() local
1714 OffsetLong = IRB.CreateAnd(OffsetLong, constToIntPtr(IntptrTy, ~AndMask)); in getShadowPtrOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp791 const uint64_t AndMask = ~(MaxAlign - 1); in allocateStackSpace() local
806 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) in allocateStackSpace()
865 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) in allocateStackSpace()
894 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) in allocateStackSpace()
2142 uint64_t AndMask = ~(MFI.getMaxAlign().value() - 1); in emitPrologue() local
2145 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)); in emitPrologue()
H A DAArch64ISelDAGToDAG.cpp751 APInt AndMask = RHSC->getAPIntValue(); in SelectShiftedRegisterFromAnd() local
753 if (!AndMask.isShiftedMask(LowZBits, MaskLen)) in SelectShiftedRegisterFromAnd()
839 uint64_t AndMask = CSD->getZExtValue(); in getExtendTypeForNode() local
841 switch (AndMask) { in getExtendTypeForNode()
2586 uint64_t AndMask = 0; in isSeveralBitsExtractOpFromShr() local
2587 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, AndMask)) in isSeveralBitsExtractOpFromShr()
2597 if (!isMask_64(AndMask >> SrlImm)) in isSeveralBitsExtractOpFromShr()
2602 MSB = llvm::Log2_64(AndMask); in isSeveralBitsExtractOpFromShr()
H A DAArch64ISelLowering.cpp20309 uint64_t AndMask = CSD->getZExtValue(); in isExtendOrShiftOperand() local
20310 return AndMask == 0xff || AndMask == 0xffff || AndMask == 0xffffffff; in isExtendOrShiftOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelDAGToDAG.cpp2759 const APInt &AndMask = ShAmt.getConstantOperandAPInt(1); in selectShiftMask() local
2764 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
2766 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask()
2772 if (!ShMask.isSubsetOf(AndMask | Known.Zero)) in selectShiftMask()
H A DRISCVISelLowering.h1039 const APInt &AndMask) const override;
H A DRISCVISelLowering.cpp22032 EVT VT, const APInt &AndMask) const { in shouldFoldSelectWithSingleBitTest()
22034 return !Subtarget.hasStdExtZbs() && AndMask.ugt(1024);
22035 return TargetLowering::shouldFoldSelectWithSingleBitTest(VT, AndMask); in getMinimumJumpTableEntries()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h896 const std::optional<APInt> &AndMask) const { in preferedOpcodeForCmpEqPiecesOfOperand() argument
3379 const APInt &AndMask) const { in shouldFoldSelectWithSingleBitTest() argument
3380 unsigned ShCt = AndMask.getBitWidth() - 1; in shouldFoldSelectWithSingleBitTest()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DLocal.cpp3859 const APInt &AndMask = *C; in collectBitParts() local
3863 unsigned NumMaskedBits = AndMask.popcount(); in collectBitParts()
3875 if (AndMask[BitIdx] == 0) in collectBitParts()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1149 const std::optional<APInt> &AndMask) const override;
H A DX86ISelLowering.cpp3366 const APInt &ShiftOrRotateAmt, const std::optional<APInt> &AndMask) const { in preferedOpcodeForCmpEqPiecesOfOperand()
3388 assert(AndMask.has_value() && "Null andmask when querying about shift+and"); in preferedOpcodeForCmpEqPiecesOfOperand()
3404 return AndMask->getSignificantBits() > 32 ? (unsigned)ISD::SRL in preferedOpcodeForCmpEqPiecesOfOperand()
3416 return AndMask->getSignificantBits() > 33 ? (unsigned)ISD::SHL : ShiftOpc; in preferedOpcodeForCmpEqPiecesOfOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp7918 encodeBitmaskPerm(const unsigned AndMask, in encodeBitmaskPerm() argument
7924 (AndMask << BITMASK_AND_SHIFT) | in encodeBitmaskPerm()
8070 unsigned AndMask = 0; in parseSwizzleBitmaskPerm() local
8086 AndMask |= Mask; in parseSwizzleBitmaskPerm()
8089 AndMask |= Mask; in parseSwizzleBitmaskPerm()
8095 Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask); in parseSwizzleBitmaskPerm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp5577 auto AndMask = B.buildConstant(S32, 0x0000ffff); in legalizePointerAsRsrcIntrin() local
5578 auto Masked = B.buildAnd(S32, HighHalf, AndMask); in legalizePointerAsRsrcIntrin()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7632 uint64_t AndMask = *MaybeAndMask; in getExtendTypeForInst() local
7633 switch (AndMask) { in getExtendTypeForInst()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp26047 SmallVector<SDValue, 16> AndMask(NumElts, DAG.getUNDEF(IntSVT)); in visitVECTOR_SHUFFLE() local
26050 AndMask[I] = Mask[I] == I ? AllOnesElt : ZeroElt; in visitVECTOR_SHUFFLE()
26062 DAG.getBuildVector(IntVT, DL, AndMask))); in visitVECTOR_SHUFFLE()
27702 const APInt &AndMask = ConstAndRHS->getAPIntValue(); in SimplifySelectCC() local
27703 if (TLI.shouldFoldSelectWithSingleBitTest(VT, AndMask)) { in SimplifySelectCC()
27704 unsigned ShCt = AndMask.getBitWidth() - 1; in SimplifySelectCC()
27705 SDValue ShlAmt = DAG.getShiftAmountConstant(AndMask.countl_zero(), VT, in SimplifySelectCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17744 uint32_t AndMask = static_cast<uint32_t>(AndMaskNode->getZExtValue()); in PerformShiftCombine() local
17746 if (AndMask == 255 || AndMask == 65535) in PerformShiftCombine()
17748 if (isMask_32(AndMask)) { in PerformShiftCombine()
17749 uint32_t MaskedBits = llvm::countl_zero(AndMask); in PerformShiftCombine()