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Searched refs:AndMask (Results 1 – 25 of 27) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelDAGToDAG.cpp277 const APInt &AndMask = N->getConstantOperandAPInt(1); in selectShiftMask() local
282 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
284 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask()
292 if (ShMask.isSubsetOf(AndMask | Known.Zero)) { in selectShiftMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp1472 static void printSwizzleBitmask(const uint16_t AndMask, in printSwizzleBitmask() argument
1478 uint16_t Probe0 = ((0 & AndMask) | OrMask) ^ XorMask; in printSwizzleBitmask()
1479 uint16_t Probe1 = ((BITMASK_MASK & AndMask) | OrMask) ^ XorMask; in printSwizzleBitmask()
1542 uint16_t AndMask = (Imm >> BITMASK_AND_SHIFT) & BITMASK_MASK; in printSwizzle() local
1546 if (AndMask == BITMASK_MAX && OrMask == 0 && llvm::popcount(XorMask) == 1) { in printSwizzle()
1553 } else if (AndMask == BITMASK_MAX && OrMask == 0 && XorMask > 0 && in printSwizzle()
1563 uint16_t GroupSize = BITMASK_MAX - AndMask + 1; in printSwizzle()
1579 printSwizzleBitmask(AndMask, OrMask, XorMask, O); in printSwizzle()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DAggressiveInstCombine.cpp331 const APInt *AndMask; in tryToRecognizePopCount() local
334 m_APInt(AndMask)))) { in tryToRecognizePopCount()
336 if (*AndMask == Mask55) in tryToRecognizePopCount()
341 if (!AndMask->isSubsetOf(Mask55)) in tryToRecognizePopCount()
344 APInt NeededMask = Mask55 & ~*AndMask; in tryToRecognizePopCount()
/freebsd/lib/libvgl/
H A Dvgl.h128 void VGLMouseSetImage(VGLBitmap *AndMask, VGLBitmap *OrMask);
H A Dmouse.c252 VGLMouseSetImage(VGLBitmap *AndMask, VGLBitmap *OrMask) in VGLMouseSetImage() argument
258 VGLMouseAndMask = AndMask; in VGLMouseSetImage()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineSelect.cpp124 Value *FalseVal, Value *V, const APInt &AndMask, in foldSelectICmpAnd() argument
139 if (TC.getBitWidth() != AndMask.getBitWidth()) in foldSelectICmpAnd()
152 Constant *MaskC = ConstantInt::get(SelType, AndMask); in foldSelectICmpAnd()
174 unsigned AndZeros = AndMask.logBase2(); in foldSelectICmpAnd()
189 V = Builder.CreateAnd(V, ConstantInt::get(V->getType(), AndMask)); in foldSelectICmpAnd()
775 const APInt &AndMask, bool CreateAnd, in foldSelectICmpAndBinOp() argument
781 unsigned C1Log = AndMask.logBase2(); in foldSelectICmpAndBinOp()
818 V = Builder.CreateAnd(V, ConstantInt::get(V->getType(), AndMask)); in foldSelectICmpAndBinOp()
3861 APInt AndMask; in foldSelectBitTest() local
3876 AndMask = *AndRHS; in foldSelectBitTest()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVInstructionSelector.cpp285 APInt AndMask; in selectShiftMask() local
301 if (mi_match(ShAmtReg, *MRI, m_GAnd(m_Reg(AndSrcReg), m_ICst(AndMask)))) { in selectShiftMask()
302 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
303 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask()
309 if (ShMask.isSubsetOf(AndMask | Known.Zero)) in selectShiftMask()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp760 uint64_t AndMask = MaskNode->getZExtValue(); in detectOrAndInsertion() local
761 if (InsertMask & AndMask) in detectOrAndInsertion()
767 if (Used != (AndMask | InsertMask)) { in detectOrAndInsertion()
769 if (Used != (AndMask | InsertMask | Known.Zero.getZExtValue())) in detectOrAndInsertion()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Instrumentation/
H A DDataFlowSanitizer.cpp282 uint64_t AndMask; member
1901 uint64_t AndMask = MapParams->AndMask; in getShadowOffset() local
1902 if (AndMask) in getShadowOffset()
1904 IRB.CreateAnd(OffsetLong, ConstantInt::get(IntptrTy, ~AndMask)); in getShadowOffset()
H A DMemorySanitizer.cpp421 uint64_t AndMask; member
1036 CustomMapParams.AndMask = ClAndMask; in initializeModule()
1789 if (uint64_t AndMask = MS.MapParams->AndMask) in getShadowPtrOffset() local
1790 OffsetLong = IRB.CreateAnd(OffsetLong, constToIntPtr(IntptrTy, ~AndMask)); in getShadowPtrOffset()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FrameLowering.cpp827 const uint64_t AndMask = ~(MaxAlign - 1); in allocateStackSpace() local
842 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) in allocateStackSpace()
901 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) in allocateStackSpace()
930 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)) in allocateStackSpace()
2320 uint64_t AndMask = ~(MFI.getMaxAlign().value() - 1); in emitPrologue() local
2323 .addImm(AArch64_AM::encodeLogicalImmediate(AndMask, 64)); in emitPrologue()
H A DAArch64ISelDAGToDAG.cpp755 APInt AndMask = RHSC->getAPIntValue(); in SelectShiftedRegisterFromAnd() local
757 if (!AndMask.isShiftedMask(LowZBits, MaskLen)) in SelectShiftedRegisterFromAnd()
843 uint64_t AndMask = CSD->getZExtValue(); in getExtendTypeForNode() local
845 switch (AndMask) { in getExtendTypeForNode()
2686 uint64_t AndMask = 0; in isSeveralBitsExtractOpFromShr() local
2687 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, AndMask)) in isSeveralBitsExtractOpFromShr()
2697 if (!isMask_64(AndMask >> SrlImm)) in isSeveralBitsExtractOpFromShr()
2702 MSB = llvm::Log2_64(AndMask); in isSeveralBitsExtractOpFromShr()
H A DAArch64ISelLowering.cpp21050 uint64_t AndMask = CSD->getZExtValue(); in isExtendOrShiftOperand() local
21051 return AndMask == 0xff || AndMask == 0xffff || AndMask == 0xffffffff; in isExtendOrShiftOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h630 const APInt &AndMask) const override;
H A DRISCVISelDAGToDAG.cpp3111 const APInt &AndMask = ShAmt.getConstantOperandAPInt(1); in selectShiftMask() local
3116 APInt ShMask(AndMask.getBitWidth(), ShiftWidth - 1); in selectShiftMask()
3118 if (ShMask.isSubsetOf(AndMask)) { in selectShiftMask()
3124 if (!ShMask.isSubsetOf(AndMask | Known.Zero)) in selectShiftMask()
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DSimplifyCFG.cpp6240 APInt AndMask = APInt::getAllOnes(MinCaseVal->getBitWidth()); in foldSwitchToSelect() local
6246 AndMask &= Case->getValue(); in foldSwitchToSelect()
6250 if (!AndMask.isZero() && Known.getMaxValue().uge(AndMask)) { in foldSwitchToSelect()
6252 unsigned FreeBits = Known.countMaxActiveBits() - AndMask.popcount(); in foldSwitchToSelect()
6257 Value *And = Builder.CreateAnd(Condition, AndMask); in foldSwitchToSelect()
6259 And, Constant::getIntegerValue(And->getType(), AndMask)); in foldSwitchToSelect()
H A DLocal.cpp3951 const APInt &AndMask = *C; in collectBitParts() local
3955 unsigned NumMaskedBits = AndMask.popcount(); in collectBitParts()
3967 if (AndMask[BitIdx] == 0) in collectBitParts()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetLowering.h926 const std::optional<APInt> &AndMask) const { in preferedOpcodeForCmpEqPiecesOfOperand() argument
3482 const APInt &AndMask) const { in shouldFoldSelectWithSingleBitTest() argument
3483 unsigned ShCt = AndMask.getBitWidth() - 1; in shouldFoldSelectWithSingleBitTest()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.h1235 const std::optional<APInt> &AndMask) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp8342 encodeBitmaskPerm(const unsigned AndMask, in encodeBitmaskPerm() argument
8348 (AndMask << BITMASK_AND_SHIFT) | in encodeBitmaskPerm()
8491 unsigned AndMask = 0; in parseSwizzleBitmaskPerm() local
8507 AndMask |= Mask; in parseSwizzleBitmaskPerm()
8510 AndMask |= Mask; in parseSwizzleBitmaskPerm()
8516 Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask); in parseSwizzleBitmaskPerm()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp911 SDValue AndMask = FirstOperand.getOpcode() == ISD::AND in performORCombine() local
914 if (!(CN = dyn_cast<ConstantSDNode>(AndMask)) || in performORCombine()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp3961 APInt AndMask; in foldSubCtlzNot() local
3981 m_ConstInt(AndMask)))) { in foldSubCtlzNot()
3985 if (!(AndMask.isMask(AndMaskWidth) && XorMask.countr_one() >= AndMaskWidth)) in foldSubCtlzNot()
27139 SmallVector<SDValue, 16> AndMask(NumElts, DAG.getUNDEF(IntSVT)); in visitVECTOR_SHUFFLE() local
27142 AndMask[I] = Mask[I] == I ? AllOnesElt : ZeroElt; in visitVECTOR_SHUFFLE()
27154 DAG.getBuildVector(IntVT, DL, AndMask))); in visitVECTOR_SHUFFLE()
28824 const APInt &AndMask = ConstAndRHS->getAPIntValue(); in SimplifySelectCC() local
28825 if (TLI.shouldFoldSelectWithSingleBitTest(VT, AndMask)) { in SimplifySelectCC()
28826 unsigned ShCt = AndMask.getBitWidth() - 1; in SimplifySelectCC()
28827 SDValue ShlAmt = DAG.getShiftAmountConstant(AndMask.countl_zero(), VT, in SimplifySelectCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp7810 uint64_t AndMask = *MaybeAndMask; in getExtendTypeForInst() local
7811 switch (AndMask) { in getExtendTypeForInst()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPULegalizerInfo.cpp5683 auto AndMask = B.buildConstant(S32, 0x0000ffff); in legalizePointerAsRsrcIntrin() local
5684 auto Masked = B.buildAnd(S32, HighHalf, AndMask); in legalizePointerAsRsrcIntrin()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp17822 uint32_t AndMask = static_cast<uint32_t>(AndMaskNode->getZExtValue()); in PerformShiftCombine() local
17824 if (AndMask == 255 || AndMask == 65535) in PerformShiftCombine()
17826 if (isMask_32(AndMask)) { in PerformShiftCombine()
17827 uint32_t MaskedBits = llvm::countl_zero(AndMask); in PerformShiftCombine()

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