| /freebsd/sys/contrib/libsodium/packaging/nuget/ |
| H A D | package.gsl | 139 …And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov201…
144 …And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov201…
149 …And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov201…
154 …And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov201…
161 … And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov20…
166 … And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov20…
171 … And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov20…
176 … And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov20…
183 …And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov201…
188 …And ('$\(PlatformToolset)' == '$(package.platformtoolset)' Or '$\(PlatformToolset)' == 'CTP_Nov201…
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIOptimizeExecMaskingPreRA.cpp | 100 const MachineInstr &Sel, const MachineInstr &And) { in isDefBetween() argument
101 SlotIndex AndIdx = LIS->getInstructionIndex(And).getRegSlot(); in isDefBetween()
139 auto *And = in optimizeVcndVcmpPair() local
141 if (!And || And->getOpcode() != AndOpc || in optimizeVcndVcmpPair()
142 !And->getOperand(1).isReg() || !And->getOperand(2).isReg()) in optimizeVcndVcmpPair()
145 MachineOperand *AndCC = &And->getOperand(1); in optimizeVcndVcmpPair()
149 AndCC = &And->getOperand(2); in optimizeVcndVcmpPair()
152 } else if (And->getOperand(2).getReg() != Register(ExecReg)) { in optimizeVcndVcmpPair()
156 auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS); in optimizeVcndVcmpPair()
159 Cmp->getParent() != And->getParent()) in optimizeVcndVcmpPair()
[all …]
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| H A D | SILowerControlFlow.cpp | 251 MachineInstr *And = in emitIf() local
256 LV->replaceKillInstruction(Cond.getReg(), MI, *And); in emitIf()
258 setImpSCCDefDead(*And, true); in emitIf()
295 LIS->ReplaceMachineInstrInMaps(MI, *And); in emitIf()
338 MachineInstr *And = BuildMI(MBB, ElsePt, DL, TII->get(AndOpc), DstReg) in emitElse() local
364 LIS->InsertMachineInstrInMaps(*And); in emitElse()
396 MachineInstr *And = nullptr, *Or = nullptr; in emitIfBreak() local
400 And = BuildMI(MBB, &MI, DL, TII->get(AndOpc), AndReg) in emitIfBreak()
404 LV->replaceKillInstruction(MI.getOperand(1).getReg(), MI, *And); in emitIfBreak()
420 if (And) { in emitIfBreak()
[all …]
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| /freebsd/tests/sys/geom/class/uzip/etalon/ |
| H A D | etalon.txt | 12 And the mome raths outgrabe.
22 And stood awhile in thought.
24 And, as in uffish thought he stood,
27 And burbled as it came!
29 One, two! One, two! And through and through
34 "And, has thou slain the Jabberwock?
42 And the mome raths outgrabe.
|
| /freebsd/contrib/one-true-awk/testdir/ |
| H A D | bib | 2 And the earth was without form, and void; and darkness was upon the face of the deep. And the Spiri…
3 And God said, Let there be light: and there was light.
4 And God saw the light, that it was good: and God divided the light from the darkness.
5 And God called the light Day, and the darkness he called Night. And the evening and the morning wer…
6 And God said, Let there be a firmament in the midst of the waters, and let it divide the waters fro…
7 And God made the firmament, and divided the waters which were under the firmament from the waters w…
8 And God called the firmament Heaven. And the evening and the morning were the second day.
9 And God said, Let the waters under the heaven be gathered together unto one place, and let the dry …
10 And God called the dry land Earth; and the gathering together of the waters called he Seas: and God…
11 And God said, Let the earth bring forth grass, the herb yielding seed, and the fruit tree yielding …
[all …]
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| /freebsd/contrib/llvm-project/clang/lib/Analysis/ |
| H A D | ThreadSafetyLogical.cpp | 44 case LExpr::And: in implies()
49 return RNeg ? RightOrOperator(cast<And>(RHS)) in implies()
50 : RightAndOperator(cast<And>(RHS)); in implies()
69 case LExpr::And: in implies()
74 return LNeg ? LeftAndOperator(cast<And>(LHS)) in implies()
75 : LeftOrOperator(cast<And>(LHS)); in implies()
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| /freebsd/contrib/llvm-project/llvm/lib/Analysis/ |
| H A D | GuardUtils.cpp | 96 auto *And = dyn_cast<Instruction>(Cond); in parseWidenableBranch()
97 if (!And) in parseWidenableBranch()
103 WC = &And->getOperandUse(0); in parseWidenableBranch()
104 C = &And->getOperandUse(1); in parseWidenableBranch()
110 WC = &And->getOperandUse(1); in parseWidenableBranch()
111 C = &And->getOperandUse(0); in parseWidenableBranch()
94 auto *And = dyn_cast<Instruction>(Cond); parseWidenableBranch() local
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| /freebsd/contrib/llvm-project/clang/include/clang/Analysis/Analyses/ |
| H A D | ThreadSafetyLogical.h | 25 And, enumerator
68 class And : public BinOp {
70 And(LExpr *LHS, LExpr *RHS) : BinOp(LHS, RHS, LExpr::And) {} in And() function
72 static bool classof(const LExpr *E) { return E->kind() == LExpr::And; } in classof()
|
| /freebsd/usr.bin/diff/tests/ |
| H A D | unified_9999.out | 7 - * And another bla
8 + * And another bla
10 - * And yet another
|
| H A D | unified_p.out | 7 - * And another bla
8 + * And another bla
10 - * And yet another
|
| H A D | group-format.out | 5 * And another bla
7 * And another bla
11 * And yet another
|
| H A D | simple_p.out | 8 ! * And another bla
10 ! * And yet another
23 ! * And another bla
|
| H A D | unified_c9999.out | 8 ! * And another bla
10 ! * And yet another
24 ! * And another bla
|
| H A D | ifdef.out | 5 * And another bla
7 * And another bla
11 * And yet another
|
| H A D | simple_i.out | 2 < * And another bla
4 > * And another bla
|
| H A D | input_c1.in | 4 * And another bla
6 * And yet another
|
| /freebsd/contrib/kyua/doc/ |
| H A D | manbuild_test.sh | 59 And nothing more.
65 And nothing more.
76 And nothing more.
82 And nothing more.
119 And done!
135 And done!
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 688 auto And = [&](auto Lhs, auto Rhs) -> std::pair<Value *, uint8_t> { in simplifyTernarylogic() local
696 auto Nand = [&](auto Lhs, auto Rhs) { return Not(And(Lhs, Rhs)); }; in simplifyTernarylogic()
732 Res = And(Nor(A, B), C); in simplifyTernarylogic()
740 Res = And(Nor(A, C), B); in simplifyTernarylogic()
752 Res = Nor(A, And(B, C)); in simplifyTernarylogic()
787 Res = And(A, Nor(B, C)); in simplifyTernarylogic()
799 Res = Nor(And(A, C), B); in simplifyTernarylogic()
807 Res = Nor(And(A, B), C); in simplifyTernarylogic()
811 Res = Xor(Xor(A, B), And(Nand(A, B), C)); in simplifyTernarylogic()
823 Res = And(Nand(A, B), Xnor(B, C)); in simplifyTernarylogic()
[all …]
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| /freebsd/crypto/openssl/doc/designs/quic-design/ |
| H A D | quic-overview.md | 47 Timer And Event Queue
64 Record Layer and ACK frames from the ACK Handling And Loss Detector
72 type. Flow Controller And Statistics Collector is consulted for decisions
111 The module is called by the TX Packetizer and the ACK Handling And
114 ACK Handling And Loss Detector
126 Path And Conn Demultiplexer
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPatternsHVX.td | 393 def: OpR_RR_pat<V6_vand, And, VecI8, HVI8>;
394 def: OpR_RR_pat<V6_vand, And, VecI16, HVI16>;
395 def: OpR_RR_pat<V6_vand, And, VecI32, HVI32>;
812 def: OpR_RR_pat<V6_pred_and, And, VecQ8, HQ8>;
813 def: OpR_RR_pat<V6_pred_and, And, VecQ16, HQ16>;
814 def: OpR_RR_pat<V6_pred_and, And, VecQ32, HQ32>;
822 def: OpR_RR_pat<V6_pred_and_n, VNot2<And, qnot>, VecQ8, HQ8>;
823 def: OpR_RR_pat<V6_pred_and_n, VNot2<And, qnot>, VecQ16, HQ16>;
824 def: OpR_RR_pat<V6_pred_and_n, VNot2<And, qnot>, VecQ32, HQ32>;
839 def: AccRRR_pat<V6_veqb_and, And, seteq, HQ8, HVI8, HVI8>;
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | nvidia,tegra210-car.txt | 1 NVIDIA Tegra210 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
| H A D | nvidia,tegra30-car.txt | 1 NVIDIA Tegra30 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
| H A D | nvidia,tegra114-car.txt | 1 NVIDIA Tegra114 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
| H A D | nvidia,tegra20-car.txt | 1 NVIDIA Tegra20 Clock And Reset Controller
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineAtomicRMW.cpp | 45 case AtomicRMWInst::And: in isIdempotentRMW()
89 case AtomicRMWInst::And: in isSaturating()
|