92                          const MachineInstr &Sel, const MachineInstr &And) {  in isDefBetween()  argument
93   SlotIndex AndIdx = LIS->getInstructionIndex(And).getRegSlot();  in isDefBetween()
131   auto *And =  in optimizeVcndVcmpPair()  local
133   if (!And || And->getOpcode() != AndOpc ||  in optimizeVcndVcmpPair()
134       !And->getOperand(1).isReg() || !And->getOperand(2).isReg())  in optimizeVcndVcmpPair()
137   MachineOperand *AndCC = &And->getOperand(1);  in optimizeVcndVcmpPair()
141     AndCC = &And->getOperand(2);  in optimizeVcndVcmpPair()
144   } else if (And->getOperand(2).getReg() != Register(ExecReg)) {  in optimizeVcndVcmpPair()
148   auto *Cmp = TRI->findReachingDef(CmpReg, CmpSubReg, *And, *MRI, LIS);  in optimizeVcndVcmpPair()
151       Cmp->getParent() != And->getParent())  in optimizeVcndVcmpPair()
184   if (isDefBetween(*TRI, LIS, CCReg, *Sel, *And))  in optimizeVcndVcmpPair()
199                     << *And);  in optimizeVcndVcmpPair()
202       BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc),  in optimizeVcndVcmpPair()
203               And->getOperand(0).getReg())  in optimizeVcndVcmpPair()
206   MachineOperand &AndSCC = And->getOperand(3);  in optimizeVcndVcmpPair()
212   SlotIndex AndIdx = LIS->ReplaceMachineInstrInMaps(*And, *Andn2);  in optimizeVcndVcmpPair()
213   And->eraseFromParent();  in optimizeVcndVcmpPair()