| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 200 Type *AmtVT = Amt->getType(); in simplifyX86immShift() local
208 assert(AmtVT->isIntegerTy(32) && "Unexpected shift-by-immediate type"); in simplifyX86immShift()
227 assert(AmtVT->isVectorTy() && AmtVT->getPrimitiveSizeInBits() == 128 && in simplifyX86immShift()
228 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
230 unsigned NumAmtElts = cast<FixedVectorType>(AmtVT)->getNumElements(); in simplifyX86immShift()
254 assert(AmtVT->isVectorTy() && AmtVT->getPrimitiveSizeInBits() == 128 && in simplifyX86immShift()
255 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
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| H A D | X86ISelLowering.cpp | 26082 MVT AmtVT = ShAmt.getSimpleValueType(); in getTargetVShiftNode() local
26083 assert(AmtVT.isVector() && "Vector shift type mismatch"); in getTargetVShiftNode()
26084 assert(0 <= ShAmtIdx && ShAmtIdx < (int)AmtVT.getVectorNumElements() && in getTargetVShiftNode()
26089 SmallVector<int> Mask(AmtVT.getVectorNumElements(), -1); in getTargetVShiftNode()
26091 ShAmt = DAG.getVectorShuffle(AmtVT, dl, ShAmt, DAG.getUNDEF(AmtVT), Mask); in getTargetVShiftNode()
26095 if (AmtVT.getScalarSizeInBits() == 64 && in getTargetVShiftNode()
26101 AmtVT = ShAmt.getSimpleValueType(); in getTargetVShiftNode()
26108 if (AmtVT.getScalarSizeInBits() < 64) { in getTargetVShiftNode()
26116 AmtVT = MVT::v4i32; in getTargetVShiftNode()
26123 AmtVT.getVectorNumElements(), in getTargetVShiftNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 282 EVT AmtVT = Amt.getValueType(); in LowerShifts() local
283 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, in LowerShifts()
284 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); in LowerShifts()
289 EVT AmtVT = Amt.getValueType(); in LowerShifts() local
290 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, in LowerShifts()
291 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); in LowerShifts()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1580 EVT AmtVT = Amt.getValueType(); in PromoteIntRes_FunnelShift() local
1591 Amt = DAG.getNode(ISD::UREM, DL, AmtVT, Amt, in PromoteIntRes_FunnelShift()
1592 DAG.getConstant(OldBits, DL, AmtVT)); in PromoteIntRes_FunnelShift()
1612 SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, AmtVT); in PromoteIntRes_FunnelShift()
1618 Amt = DAG.getNode(ISD::ADD, DL, AmtVT, Amt, ShiftOffset); in PromoteIntRes_FunnelShift()
1632 EVT AmtVT = Amt.getValueType(); in PromoteIntRes_VPFunnelShift() local
1643 Amt = DAG.getNode(ISD::VP_UREM, DL, AmtVT, Amt, in PromoteIntRes_VPFunnelShift()
1644 DAG.getConstant(OldBits, DL, AmtVT), Mask, EVL); in PromoteIntRes_VPFunnelShift()
1665 SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, AmtVT); in PromoteIntRes_VPFunnelShift()
1671 Amt = DAG.getNode(ISD::VP_ADD, DL, AmtVT, Amt, ShiftOffset, Mask, EVL); in PromoteIntRes_VPFunnelShift()
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| H A D | DAGCombiner.cpp | 10262 EVT AmtVT = N1.getValueType(); in visitRotate() local
10263 SDValue Bits = DAG.getConstant(Bitsize, dl, AmtVT); in visitRotate()
10265 DAG.FoldConstantArithmetic(ISD::UREM, dl, AmtVT, {N1, Bits})) in visitRotate()
16077 EVT AmtVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in visitTRUNCATE() local
16079 if (AmtVT != Amt.getValueType()) { in visitTRUNCATE()
16080 Amt = DAG.getZExtOrTrunc(Amt, DL, AmtVT); in visitTRUNCATE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 9259 EVT AmtVT = Amt.getValueType(); in LowerSHL_PARTS() local
9261 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSHL_PARTS()
9262 DAG.getConstant(BitWidth, dl, AmtVT), Amt); in LowerSHL_PARTS()
9266 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSHL_PARTS()
9267 DAG.getSignedConstant(-BitWidth, dl, AmtVT)); in LowerSHL_PARTS()
9288 EVT AmtVT = Amt.getValueType(); in LowerSRL_PARTS() local
9290 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRL_PARTS()
9291 DAG.getConstant(BitWidth, dl, AmtVT), Amt); in LowerSRL_PARTS()
9295 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSRL_PARTS()
9296 DAG.getSignedConstant(-BitWidth, dl, AmtVT)); in LowerSRL_PARTS()
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