| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstCombineIntrinsic.cpp | 206 Type *AmtVT = Amt->getType(); in simplifyX86immShift() local
214 assert(AmtVT->isIntegerTy(32) && "Unexpected shift-by-immediate type"); in simplifyX86immShift()
233 assert(AmtVT->isVectorTy() && AmtVT->getPrimitiveSizeInBits() == 128 && in simplifyX86immShift()
234 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
236 unsigned NumAmtElts = cast<FixedVectorType>(AmtVT)->getNumElements(); in simplifyX86immShift()
260 assert(AmtVT->isVectorTy() && AmtVT->getPrimitiveSizeInBits() == 128 && in simplifyX86immShift()
261 cast<VectorType>(AmtVT)->getElementType() == SVT && in simplifyX86immShift()
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| H A D | X86ISelLowering.cpp | 25237 MVT AmtVT = ShAmt.getSimpleValueType(); in getTargetVShiftNode() local
25238 assert(AmtVT.isVector() && "Vector shift type mismatch"); in getTargetVShiftNode()
25239 assert(0 <= ShAmtIdx && ShAmtIdx < (int)AmtVT.getVectorNumElements() && in getTargetVShiftNode()
25244 SmallVector<int> Mask(AmtVT.getVectorNumElements(), -1); in getTargetVShiftNode()
25246 ShAmt = DAG.getVectorShuffle(AmtVT, dl, ShAmt, DAG.getUNDEF(AmtVT), Mask); in getTargetVShiftNode()
25250 if (AmtVT.getScalarSizeInBits() == 64 && in getTargetVShiftNode()
25256 AmtVT = ShAmt.getSimpleValueType(); in getTargetVShiftNode()
25263 if (AmtVT.getScalarSizeInBits() < 64) { in getTargetVShiftNode()
25271 AmtVT = MVT::v4i32; in getTargetVShiftNode()
25278 AmtVT.getVectorNumElements(), in getTargetVShiftNode()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 335 EVT AmtVT = Amt.getValueType(); in LowerShifts() local
336 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, in LowerShifts()
337 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); in LowerShifts()
342 EVT AmtVT = Amt.getValueType(); in LowerShifts() local
343 Amt = DAG.getNode(ISD::AND, dl, AmtVT, Amt, in LowerShifts()
344 DAG.getConstant(VT.getSizeInBits() - 1, dl, AmtVT)); in LowerShifts()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 1535 EVT AmtVT = Amt.getValueType(); in PromoteIntRes_FunnelShift() local
1546 Amt = DAG.getNode(ISD::UREM, DL, AmtVT, Amt, in PromoteIntRes_FunnelShift()
1547 DAG.getConstant(OldBits, DL, AmtVT)); in PromoteIntRes_FunnelShift()
1567 SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, AmtVT); in PromoteIntRes_FunnelShift()
1573 Amt = DAG.getNode(ISD::ADD, DL, AmtVT, Amt, ShiftOffset); in PromoteIntRes_FunnelShift()
1587 EVT AmtVT = Amt.getValueType(); in PromoteIntRes_VPFunnelShift() local
1598 Amt = DAG.getNode(ISD::VP_UREM, DL, AmtVT, Amt, in PromoteIntRes_VPFunnelShift()
1599 DAG.getConstant(OldBits, DL, AmtVT), Mask, EVL); in PromoteIntRes_VPFunnelShift()
1620 SDValue ShiftOffset = DAG.getConstant(NewBits - OldBits, DL, AmtVT); in PromoteIntRes_VPFunnelShift()
1626 Amt = DAG.getNode(ISD::VP_ADD, DL, AmtVT, Amt, ShiftOffset, Mask, EVL); in PromoteIntRes_VPFunnelShift()
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| H A D | DAGCombiner.cpp | 9806 EVT AmtVT = N1.getValueType(); in visitRotate() local
9807 SDValue Bits = DAG.getConstant(Bitsize, dl, AmtVT); in visitRotate()
9809 DAG.FoldConstantArithmetic(ISD::UREM, dl, AmtVT, {N1, Bits})) in visitRotate()
15029 EVT AmtVT = TLI.getShiftAmountTy(VT, DAG.getDataLayout()); in visitTRUNCATE() local
15031 if (AmtVT != Amt.getValueType()) { in visitTRUNCATE()
15032 Amt = DAG.getZExtOrTrunc(Amt, DL, AmtVT); in visitTRUNCATE()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 9113 EVT AmtVT = Amt.getValueType(); in LowerSHL_PARTS() local
9115 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSHL_PARTS()
9116 DAG.getConstant(BitWidth, dl, AmtVT), Amt); in LowerSHL_PARTS()
9120 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSHL_PARTS()
9121 DAG.getConstant(-BitWidth, dl, AmtVT)); in LowerSHL_PARTS()
9142 EVT AmtVT = Amt.getValueType(); in LowerSRL_PARTS() local
9144 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, in LowerSRL_PARTS()
9145 DAG.getConstant(BitWidth, dl, AmtVT), Amt); in LowerSRL_PARTS()
9149 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt, in LowerSRL_PARTS()
9150 DAG.getConstant(-BitWidth, dl, AmtVT)); in LowerSRL_PARTS()
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