| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRRegisterInfo.cpp | 239 unsigned AddOpc = AVR::ADIWRdK, SubOpc = AVR::SBIWRdK; in eliminateFrameIndex() local
244 AddOpc = AVR::SUBIWRdK; in eliminateFrameIndex()
256 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28) in eliminateFrameIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCExpandPseudos.cpp | 66 Register AddOpc = in expandStore() local
68 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg) in expandStore()
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| H A D | ARCRegisterInfo.cpp | 75 unsigned AddOpc = isUInt<6>(Offset) ? ARC::ADD_rru6 : ARC::ADD_rrlimm; in replaceFrameIndex() local
76 BuildMI(MBB, II, DL, TII.get(AddOpc)) in replaceFrameIndex()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVMatInt.h | 62 unsigned &ShiftAmt, unsigned &AddOpc);
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| H A D | RISCVMatInt.cpp | 506 unsigned &ShiftAmt, unsigned &AddOpc) { in generateTwoRegInstSeq() argument
523 AddOpc = RISCV::ADD; in generateTwoRegInstSeq()
531 AddOpc = RISCV::ADD_UW; in generateTwoRegInstSeq()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanUnroll.cpp | 182 unsigned AddOpc = in unrollWidenInductionByUF() local
188 VPInstruction *Add = Builder.createNaryOp(AddOpc, in unrollWidenInductionByUF()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 10807 unsigned AddOpc = 0; in genAlternativeDpCodeSequence() local
10819 AddOpc = X86::VPADDDrr; in genAlternativeDpCodeSequence()
10823 AddOpc = X86::VPADDDrr; in genAlternativeDpCodeSequence()
10827 AddOpc = X86::VPADDDZ128rr; in genAlternativeDpCodeSequence()
10831 AddOpc = X86::VPADDDZ128rr; in genAlternativeDpCodeSequence()
10839 AddOpc = X86::VPADDDYrr; in genAlternativeDpCodeSequence()
10843 AddOpc = X86::VPADDDYrr; in genAlternativeDpCodeSequence()
10847 AddOpc = X86::VPADDDZ256rr; in genAlternativeDpCodeSequence()
10851 AddOpc = X86::VPADDDZ256rr; in genAlternativeDpCodeSequence()
10859 AddOpc = X86::VPADDDZrr; in genAlternativeDpCodeSequence()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVLegalizerInfo.cpp | 835 unsigned ShiftAmt, AddOpc; in shouldBeInConstantPool() local
837 RISCVMatInt::generateTwoRegInstSeq(Imm, STI, ShiftAmt, AddOpc); in shouldBeInConstantPool()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelDAGToDAG.cpp | 224 unsigned ShiftAmt, AddOpc; in selectImm() local
226 RISCVMatInt::generateTwoRegInstSeq(Imm, Subtarget, ShiftAmt, AddOpc); in selectImm()
234 return SDValue(CurDAG->getMachineNode(AddOpc, DL, VT, Lo, SLLI), 0); in selectImm()
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| H A D | RISCVISelLowering.cpp | 6602 unsigned ShiftAmt, AddOpc; in lowerConstant() local
6604 RISCVMatInt::generateTwoRegInstSeq(Imm, Subtarget, ShiftAmt, AddOpc); in lowerConstant()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPUISelLowering.cpp | 3247 unsigned AddOpc = ZeroUndef ? ISD::ADD : ISD::UADDSAT; in LowerCTLZ_CTTZ() local
3250 OprLo = DAG.getNode(AddOpc, SL, MVT::i32, OprLo, Const32); in LowerCTLZ_CTTZ()
3252 OprHi = DAG.getNode(AddOpc, SL, MVT::i32, OprHi, Const32); in LowerCTLZ_CTTZ()
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| H A D | AMDGPURegisterBankInfo.cpp | 2749 unsigned AddOpc = in applyMappingImpl() local
2753 Y = B.buildInstr(AddOpc, {S32}, {Y, B.buildConstant(S32, 32)}); in applyMappingImpl()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 4786 unsigned AddOpc = (LoadImmOpc == ARM::MRC) ? ARM::ADDri : ARM::t2ADDri; in expandLoadStackGuardBase() local
4787 BuildMI(MBB, MI, DL, get(AddOpc), Reg) in expandLoadStackGuardBase()
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