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Searched refs:Abs (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/DebugInfo/PDB/
H A DUDTLayout.cpp120 uint32_t Abs = LayoutItemBase::tailPadding(); in tailPadding() local
124 if (Abs < ChildPadding) in tailPadding()
125 Abs = 0; in tailPadding()
127 Abs -= ChildPadding; in tailPadding()
129 return Abs; in tailPadding()
/freebsd/contrib/llvm-project/llvm/lib/MC/
H A DMCAssembler.cpp903 bool Abs = getWriter().getSubsectionsViaSymbols() in relaxLEB() local
906 if (!Abs) { in relaxLEB()
1003 bool Abs = DF.getAddrDelta().evaluateKnownAbsolute(AddrDelta, *this); in relaxDwarfLineAddr() local
1004 assert(Abs && "We created a line delta with an invalid expression"); in relaxDwarfLineAddr()
1005 (void)Abs; in relaxDwarfLineAddr()
1024 bool Abs = DF.getAddrDelta().evaluateAsAbsolute(Value, *this); in relaxDwarfCallFrameFragment() local
1025 if (!Abs) { in relaxDwarfCallFrameFragment()
1063 bool Abs = PF.getAddrDelta().evaluateKnownAbsolute(AddrDelta, *this); in relaxPseudoProbeAddr() local
1064 assert(Abs && "We created a pseudo probe with an invalid expression"); in relaxPseudoProbeAddr()
1065 (void)Abs; in relaxPseudoProbeAddr()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.h111 SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm,
H A DSIPeepholeSDWA.cpp133 bool Abs; member in __anon5b8513100111::SDWASrcOperand
141 : SDWAOperand(TargetOp, ReplacedOp), SrcSel(SrcSel_), Abs(Abs_), in SDWASrcOperand()
152 bool getAbs() const { return Abs; } in getAbs()
374 if (Abs || Neg) { in getSrcMods()
377 Mods |= Abs ? SISrcMods::ABS : 0u; in getSrcMods()
H A DR600ISelLowering.cpp1949 SDValue &Src, SDValue &Neg, SDValue &Abs, in FoldOperand() argument
1964 if (!Abs.getNode()) in FoldOperand()
1967 Abs = DAG.getTargetConstant(1, SDLoc(ParentNode), MVT::i32); in FoldOperand()
2123 SDValue &Abs = Ops[AbsIdx[i] - 1]; in PostISelFolding() local
2129 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, FakeOp, DAG)) in PostISelFolding()
2162 SDValue &Abs = (AbsIdx[i] > -1) ? Ops[AbsIdx[i] - 1] : FakeAbs; in PostISelFolding() local
2172 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG)) in PostISelFolding()
/freebsd/contrib/llvm-project/compiler-rt/lib/sanitizer_common/
H A Dsanitizer_stackdepot.cpp80 Abs(common_flags()->compress_stack_depot))); in CompressStackStore()
H A Dsanitizer_common.h498 constexpr T Abs(T a) { in Abs() function
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DExpandFp.cpp172 Value *Abs = Builder.CreateAnd(ARep, SignificandMask); in expandFPToI() local
173 Value *Or = Builder.CreateOr(Abs, ImplicitBit); in expandFPToI()
/freebsd/usr.bin/ee/nls/de_DE.ISO8859-1/
H A Dee.msg14 5 "Automatische Abs�tze "
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/AsmParser/
H A DAMDGPUAsmParser.cpp80 bool Abs = false; member
86 bool hasFPModifiers() const { return Abs || Neg; } in hasFPModifiers()
92 Operand |= Abs ? SISrcMods::ABS : 0u; in getFPModifiersOperand()
1255 OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext; in operator <<()
2280 if (Imm.Mods.Abs) { in applyInputFPModifiers()
3461 bool Abs, SP3Abs; in parseRegOrImmWithFPInputMods() local
3478 Abs = trySkipId("abs"); in parseRegOrImmWithFPInputMods()
3479 if (Abs && !skipToken(AsmToken::LParen, "expected left paren after abs")) in parseRegOrImmWithFPInputMods()
3496 if (Abs && SP3Abs) in parseRegOrImmWithFPInputMods()
3506 return (SP3Neg || Neg || SP3Abs || Abs || Lit || Lit64) in parseRegOrImmWithFPInputMods()
[all …]
/freebsd/contrib/llvm-project/lld/ELF/
H A DConfig.h122 enum class Target2Policy { Abs, Rel, GotRel }; enumerator
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp9283 auto Abs = MIRBuilder.buildAnd(IntTy, AsInt, ValueMaskC); in lowerISFPCLASS() local
9285 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_NE, DstTy, AsInt, Abs); in lowerISFPCLASS()
9297 appendToRes(MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_ULT, DstTy, Abs, in lowerISFPCLASS()
9307 auto Cmp = MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_ULT, DstTy, Abs, in lowerISFPCLASS()
9333 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, DstTy, Abs, ZeroC)); in lowerISFPCLASS()
9342 auto V = (PartialCheck == fcPosSubnormal) ? AsInt : Abs; in lowerISFPCLASS()
9359 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_EQ, DstTy, Abs, InfC)); in lowerISFPCLASS()
9373 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_UGT, DstTy, Abs, InfC)); in lowerISFPCLASS()
9376 appendToRes(MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_UGE, DstTy, Abs, in lowerISFPCLASS()
9382 MIRBuilder.buildICmp(CmpInst::Predicate::ICMP_UGT, DstTy, Abs, InfC); in lowerISFPCLASS()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineMulDivRem.cpp542 Value *Abs = Builder.CreateBinaryIntrinsic( in visitMul() local
544 Abs->takeName(&I); in visitMul()
545 return replaceInstUsesWith(I, Abs); in visitMul()
H A DInstCombineCalls.cpp2123 Value *Abs = Builder.CreateBinaryIntrinsic( in visitCallInst() local
2130 Abs = Builder.CreateNeg(Abs, "nabs", IntMinIsPoison); in visitCallInst()
2131 return replaceInstUsesWith(CI, Abs); in visitCallInst()
H A DInstCombineSelect.cpp1273 Value *Abs = in canonicalizeSPF() local
1277 return IC.Builder.CreateNeg(Abs); // Always without NSW flag! in canonicalizeSPF()
1278 return Abs; in canonicalizeSPF()
H A DInstCombineAndOrXor.cpp5202 if (Instruction *Abs = canonicalizeAbs(I, Builder)) in visitXor() local
5203 return Abs; in visitXor()
/freebsd/contrib/llvm-project/llvm/tools/llvm-nm/
H A Dllvm-nm.cpp1293 bool Abs = ((EFlags & MachO::EXPORT_SYMBOL_FLAGS_KIND_MASK) == in dumpSymbolsFromDLInfoMachO() local
1300 if (Abs) { in dumpSymbolsFromDLInfoMachO()
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DARM.cpp144 if (ctx.arg.target2 == Target2Policy::Abs) in getRelExpr()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2907 SDValue Abs = Signed ? DAG.getNode(ISD::ABS, dl, InpTy, Op0) : Op0; in ExpandHvxIntToFp() local
2908 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, InpTy, Abs); in ExpandHvxIntToFp()
2910 SDValue Frac0 = DAG.getNode(ISD::SHL, dl, InpTy, {Abs, NLeft}); in ExpandHvxIntToFp()
H A DHexagonPatternsHVX.td955 // Abs = vxor(v27,v29) ; ^ masks
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp2612 SDValue Abs = DAG.getNode(ISD::AND, dl, AsIntVT, AsInt, SignMask); in expandFrexp() local
2615 DAG.getNode(ISD::ADD, dl, AsIntVT, Abs, NegSmallestNormalizedInt); in expandFrexp()
2620 DAG.getSetCC(dl, SetCCVT, Abs, SmallestNormalizedInt, ISD::SETULT); in expandFrexp()
2633 DAG.getNode(ISD::SELECT, dl, AsIntVT, IsDenormal, ExpMaskScaled, Abs); in expandFrexp()
H A DTargetLowering.cpp8959 SDValue Abs = DAG.getNode(ISD::FABS, DL, OperandVT, Op); in expandIS_FPCLASS() local
8962 return DAG.getSetCC(DL, ResultVT, Abs, Inf, in expandIS_FPCLASS()
8995 SDValue Abs = DAG.getNode(ISD::FABS, DL, OperandVT, Op); in expandIS_FPCLASS() local
8998 return DAG.getSetCC(DL, ResultVT, Abs, SmallestNormal, in expandIS_FPCLASS()
9019 SDValue Abs = DAG.getNode(ISD::FABS, DL, OperandVT, Op); in expandIS_FPCLASS() local
9020 SDValue IsFinite = DAG.getSetCC(DL, ResultVT, Abs, Inf, IsFiniteOp); in expandIS_FPCLASS()
9022 DAG.getSetCC(DL, ResultVT, Abs, SmallestNormal, IsNormalOp); in expandIS_FPCLASS()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsNVVM.td887 // Abs
895 // Abs, Neg bf16, bf16x2
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp517 unsigned Abs = Float64 ? WebAssembly::ABS_F64 : WebAssembly::ABS_F32; in LowerFPToInt() local
564 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg); in LowerFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/DirectX/
H A DDXIL.td404 def Abs : DXILOp<6, unary> {

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