Home
last modified time | relevance | path

Searched refs:AVL (Results 1 – 23 of 23) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVVPISelLowering.cpp24 SDValue AVL = in splitMaskArithmetic() local
28 SDValue LoA = CDAG.getUnpack(MVT::v256i1, A, PackElem::Lo, AVL); in splitMaskArithmetic()
29 SDValue HiA = CDAG.getUnpack(MVT::v256i1, A, PackElem::Hi, AVL); in splitMaskArithmetic()
30 SDValue LoB = CDAG.getUnpack(MVT::v256i1, B, PackElem::Lo, AVL); in splitMaskArithmetic()
31 SDValue HiB = CDAG.getUnpack(MVT::v256i1, B, PackElem::Hi, AVL); in splitMaskArithmetic()
35 return CDAG.getPack(MVT::v512i1, LoRes, HiRes, AVL); in splitMaskArithmetic()
63 SDValue AVL; in lowerToVVP() local
73 AVL = Op->getOperand(*AVLIdx); in lowerToVVP()
77 if (!AVL) in lowerToVVP()
78 AVL in lowerToVVP()
132 SDValue AVL = getNodeAVL(Op); lowerVVP_LOAD_STORE() local
270 SDValue AVL = getAnnotatedNodeAVL(Op).first; lowerVVP_GATHER_SCATTER() local
404 auto AVL = getNodeAVL(Op); legalizePackedAVL() local
[all...]
H A DVECustomDAG.cpp214 bool isLegalAVL(SDValue AVL) { return AVL->getOpcode() == VEISD::LEGALAVL; } in isLegalAVL() argument
396 SDValue AVL = getNodeAVL(Op); in getAnnotatedNodeAVL() local
397 if (!AVL) in getAnnotatedNodeAVL()
399 if (isLegalAVL(AVL)) in getAnnotatedNodeAVL()
400 return {AVL->getOperand(0), true}; in getAnnotatedNodeAVL()
401 return {AVL, false}; in getAnnotatedNodeAVL()
414 auto AVL = getConstant(MaskVT.getVectorNumElements(), MVT::i32); in getConstantMask() local
415 auto Res = getNode(VEISD::VEC_BROADCAST, MaskVT, {TrueVal, AVL}); in getConstantMask()
423 SDValue AVL) const { in getMaskBroadcast()
440 DAG.getNode(VEISD::VEC_BROADCAST, DL, CmpVecTy, {CmpElem, AVL}); in getMaskBroadcast()
[all …]
H A DVECustomDAG.h77 bool isLegalAVL(SDValue AVL);
137 SDValue AVL; member
138 VETargetMasks(SDValue Mask = SDValue(), SDValue AVL = SDValue())
139 : Mask(Mask), AVL(AVL) {} in Mask()
185 SDValue VectorV, SDValue Mask, SDValue AVL,
190 SDValue getUnpack(EVT DestVT, SDValue Vec, PackElem Part, SDValue AVL) const;
191 SDValue getPack(EVT DestVT, SDValue LoVec, SDValue HiVec, SDValue AVL) const;
202 SDValue getMaskBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const;
203 SDValue getBroadcast(EVT ResultVT, SDValue Scalar, SDValue AVL) const;
206 SDValue annotateLegalAVL(SDValue AVL) const;
[all …]
H A DVEISelLowering.cpp1832 auto AVL = CDAG.getConstant(NumEls, MVT::i32); in lowerBUILD_VECTOR() local
1833 return CDAG.getBroadcast(ResultVT, ScalarV, AVL); in lowerBUILD_VECTOR()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVInstrInfoVSDPatterns.td50 (load_instr (m.Mask (IMPLICIT_DEF)), GPR:$rs1, m.AVL,
54 (store_instr VR:$rs2, GPR:$rs1, m.AVL, m.Log2SEW)>;
133 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
136 vti.LMul, vti.AVL, vti.RegClass,
149 vti.LMul, vti.AVL, vti.RegClass,
208 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
211 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
223 vti.LMul, vti.AVL, vti.RegClass, isSEWAware>;
226 vti.Log2SEW, vti.LMul, vti.AVL, vti.RegClass,
245 fvti.AVL, fvti.Log2SEW, TA_MA)>;
[all …]
H A DRISCVInstrInfoVPseudos.td86 def AVL : RegisterOperand<GPRNoX0> {
109 // rd | rs1 | AVL value | Effect on vl
261 def VLOpFrag : PatFrag<(ops), (XLenVT (VLOp (XLenVT AVL:$vl)))>;
264 // We can't use X0 register because the AVL operands use GPRNoX0.
295 // The pattern fragment which produces the AVL operand, representing the
297 OutPatFrag AVL = VLMax;
417 // The pattern fragment which produces the AVL operand, representing the
420 OutPatFrag AVL = VLMax;
789 (ins RetClass:$dest, GPRMemZeroOffset:$rs1, AVL:$vl, sewop:$sew,
807 VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
[all …]
H A DRISCVInstrInfoZvk.td234 (ins RetClass:$rd, OpClass:$rs2, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
251 AVL:$vl, sew:$sew, vec_policy:$policy), []>,
597 vti.AVL, vti.Log2SEW, TA_MA)>;
621 vti.AVL, vti.Log2SEW, TA_MA)>;
629 vti.AVL, vti.Log2SEW, TA_MA)>;
636 vti.AVL, vti.Log2SEW, TA_MA)>;
677 vti.AVL, vti.Log2SEW, TA_MA)>;
693 vti.AVL, vti.Log2SEW, TA_MA)>;
700 vti.AVL, vti.Log2SEW, TA_MA)>;
707 vti.AVL, vti.Log2SEW, TA_MA)>;
H A DRISCVInstrInfoXSf.td248 AVL:$vl, sew:$sew), []>,
260 AVL:$vl, sew:$sew), []>,
273 AVL:$vl, sew:$sew), []>,
285 AVL:$vl, sew:$sew), []>,
298 AVL:$vl, sew:$sew), []>,
311 AVL:$vl, sew:$sew), []>,
H A DRISCVVectorPeephole.cpp229 if (auto VLen = ST->getRealVLen(), AVL = getConstant(VL); in convertToVLMAX() local
230 VLen && AVL && (*VLen * LMULFixed) / SEW == *AVL * 8) { in convertToVLMAX()
H A DRISCVInsertVSETVLI.cpp1631 auto &AVL = MI.getOperand(1); in canMutatePriorConfig() local
1635 if (AVL.isReg() && AVL.getReg() != RISCV::X0) { in canMutatePriorConfig()
1636 VNInfo *VNI = getVNInfoFromReg(AVL.getReg(), MI, LIS); in canMutatePriorConfig()
1637 VNInfo *PrevVNI = getVNInfoFromReg(AVL.getReg(), PrevMI, LIS); in canMutatePriorConfig()
H A DRISCVInstrInfoXRivos.td165 (ins m.vrclass:$rs1, GPR:$rs2, uimm5:$idx, AVL:$vl,
H A DRISCVInstrInfoXAndes.td454 AVL:$vl, sew:$sew, vec_policy:$policy), []>,
470 VMaskOp:$vm, AVL:$vl, sew:$sew, vec_policy:$policy), []>,
H A DRISCVISelDAGToDAG.cpp504 uint64_t AVL = C->getZExtValue(); in selectVSETVLI() local
505 if (isUInt<5>(AVL)) { in selectVSETVLI()
506 SDValue VLImm = CurDAG->getTargetConstant(AVL, DL, XLenVT); in selectVSETVLI()
H A DRISCVISelLowering.cpp10371 SDValue AVL = getVLOperand(Op); in lowerVectorIntrinsicScalars() local
10375 if (isa<ConstantSDNode>(AVL)) { in lowerVectorIntrinsicScalars()
10379 uint64_t AVLInt = AVL->getAsZExtVal(); in lowerVectorIntrinsicScalars()
10400 SDValue VL = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, SETVL, AVL, in lowerVectorIntrinsicScalars()
10445 DAG.getUNDEF(VT), AVL); in lowerVectorIntrinsicScalars()
10449 MaskedOff, AVL); in lowerVectorIntrinsicScalars()
10497 SDValue AVL = DAG.getNode(ISD::ZERO_EXTEND, DL, XLenVT, N->getOperand(1)); in lowerGetVectorLength() local
10501 DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, XLenVT, ID, AVL, Sew, LMul); in lowerGetVectorLength()
11184 static bool isNonZeroAVL(SDValue AVL) { in isNonZeroAVL() argument
11185 auto *RegisterAVL = dyn_cast<RegisterSDNode>(AVL); in isNonZeroAVL()
[all …]
/freebsd/contrib/ncurses/
H A DAUTHORS37 AVL Alexander V Lukyanov
/freebsd/sys/contrib/edk2/Include/Library/
H A DBaseLib.h5546 UINT32 AVL : 1; member
5644 UINT32 AVL : 1; ///< Available for use by system software member
5701 UINT32 AVL : 1; ///< Available for use by system software member
/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DVPlanTransforms.cpp2329 VPValue *AVL = Builder.createNaryOp( in tryAddExplicitVectorLength() local
2335 VPValue *Cmp = Builder.createICmp(ICmpInst::ICMP_ULT, AVL, AVLSafe); in tryAddExplicitVectorLength()
2336 AVL = Builder.createSelect(Cmp, AVL, AVLSafe, DebugLoc(), "safe_avl"); in tryAddExplicitVectorLength()
2338 auto *VPEVL = Builder.createNaryOp(VPInstruction::ExplicitVectorLength, AVL, in tryAddExplicitVectorLength()
H A DLoopIdiomVectorize.cpp552 Value *AVL = Builder.CreateSub(ExtEnd, VectorIndexPhi, "avl", /*HasNUW=*/true, in createPredicatedFindMismatch() local
559 {I64Type}, {AVL, VF, Builder.getTrue()}); in createPredicatedFindMismatch()
H A DVPlanRecipes.cpp656 Value *AVL = State.get(getOperand(0), /*IsScalar*/ true); in generate() local
658 assert(AVL->getType()->isIntegerTy() && in generate()
666 {AVL, VFArg, State.Builder.getTrue()}); in generate()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsRISCV.td148 /* AVL */ [LLVMMatchType<0>,
/freebsd/contrib/one-true-awk/testdir/
H A Dfunstack.ok1126 Retrieval Using AVL Trees . . . . . . . 843--843
1499 Caxton C. Foster A Generalization of AVL Trees . . . . . 513--517
H A Dfunstack.in8194 title = "On {Foster}'s Information Storage and Retrieval Using {AVL} Trees",
8208 …keywords = "(mathematical); AVL trees; binary trees; file organisation; information retrieval;…
11203 title = "A Generalization of {AVL} Trees",
11214 …AVL trees is proposed in which imbalances up to (triangle shape) is a small integer. An experiment…
11220 …keywords = "AVL trees; balanced trees; file organisation; generalisation; information retrieva…
17657 …is shown that the only statistic of HB left bracket 1 right bracket trees (AVL trees) that is a fu…
20373 …AVL and extensions), weight-balance (i.e. BB and WB), and total restructuring-for building balance…
20380 …keywords = "analysis of algorithms; AVL trees; binary search trees; computer programming --- S…
22579 …keywords = "AVL trees; balanced trees; binary search; computer programming; dynamic balancing",
23144 …AVL tree in that only one bit of balancing information is required (two bits are required for the …
[all …]
/freebsd/share/misc/
H A Dusb_vendors1353 0961 AVL Flash Card Reader