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Searched refs:ARMSubtarget (Results 1 – 25 of 59) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMSubtarget.cpp73 ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU, in initializeSubtargetDependencies()
80 ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU, in initializeFrameLowering()
82 ARMSubtarget &STI = initializeSubtargetDependencies(CPU, FS); in initializeFrameLowering()
89 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, in ARMSubtarget() function in ARMSubtarget
119 const CallLowering *ARMSubtarget::getCallLowering() const { in getCallLowering()
123 InstructionSelector *ARMSubtarget::getInstructionSelector() const { in getInstructionSelector()
127 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const { in getLegalizerInfo()
131 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const { in getRegBankInfo()
135 bool ARMSubtarget::isXRaySupported() const { in isXRaySupported()
140 void ARMSubtarget::initializeEnvironment() { in initializeEnvironment()
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H A DARMSLSHardening.cpp38 const ARMSubtarget *ST;
70 static void insertSpeculationBarrier(const ARMSubtarget *ST, in insertSpeculationBarrier()
95 ST = &MF.getSubtarget<ARMSubtarget>(); in runOnMachineFunction()
178 ComdatThunks &= !MF.getSubtarget<ARMSubtarget>().hardenSlsNoComdat(); in mayUseThunk()
179 return MF.getSubtarget<ARMSubtarget>().hardenSlsBlr(); in mayUseThunk()
194 !MF.getSubtarget<ARMSubtarget>().isThumb()) || in insertThunks()
196 MF.getSubtarget<ARMSubtarget>().isThumb())) in insertThunks()
201 const ARMSubtarget *ST = &MF.getSubtarget<ARMSubtarget>(); in insertThunks()
221 const TargetInstrInfo *TII = MF.getSubtarget<ARMSubtarget>().getInstrInfo(); in populateThunk()
242 insertSpeculationBarrier(&MF.getSubtarget<ARMSubtarget>(), *Entry, in populateThunk()
H A DARMBaseRegisterInfo.cpp64 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>(); in getCalleeSavedRegs()
133 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); in getCallPreservedMask()
160 assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() && in getTLSCallPreservedMask()
167 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); in getSjLjDispatchPreservedMask()
177 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); in getThisReturnPreservedMask()
201 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); in getReservedRegs()
242 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); in isInlineAsmReadOnlyReg()
270 if (MF.getSubtarget<ARMSubtarget>().hasNEON()) in getLargestLegalSuperClass()
276 if (MF.getSubtarget<ARMSubtarget>().hasMVEIntegerOps()) in getLargestLegalSuperClass()
301 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); in getRegPressureLimit()
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H A DARMTargetMachine.cpp277 Allocator, F, static_cast<const ARMSubtarget *>(STI)); in createMachineFunctionInfo()
280 const ARMSubtarget *
313 I = std::make_unique<ARMSubtarget>(TargetTriple, CPU, FS, *this, isLittle, in getSubtargetImpl()
361 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>(); in createMachineScheduler()
371 const ARMSubtarget &ST = C->MF->getSubtarget<ARMSubtarget>(); in createPostMachineScheduler()
432 const auto &ST = this->TM->getSubtarget<ARMSubtarget>(F); in addIRPasses()
564 return this->TM->getSubtarget<ARMSubtarget>(F).hasMinSize() || in addPreSched2()
565 this->TM->getSubtarget<ARMSubtarget>(F).restrictIT(); in addPreSched2()
569 return !MF.getSubtarget<ARMSubtarget>().isThumb1Only(); in addPreSched2()
591 return MF.getSubtarget<ARMSubtarget>().isThumb2(); in addPreEmitPass()
H A DThumbRegisterInfo.cpp17 #include "ARMSubtarget.h"
45 if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only()) in getLargestLegalSuperClass()
56 if (!MF.getSubtarget<ARMSubtarget>().isThumb1Only()) in getPointerRegClass()
68 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); in emitThumb1LoadConstPool()
108 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>(); in emitLoadConstPool()
130 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>(); in emitThumbRegPlusImmInReg()
431 assert(MBB.getParent()->getSubtarget<ARMSubtarget>() in rewriteFrameIndex()
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H A DARMSelectionDAGInfo.cpp41 const ARMSubtarget &Subtarget = in EmitSpecializedLibcall()
42 DAG.getMachineFunction().getSubtarget<ARMSubtarget>(); in EmitSpecializedLibcall()
141 static bool shouldGenerateInlineTPLoop(const ARMSubtarget &Subtarget, in shouldGenerateInlineTPLoop()
172 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemcpy()
173 DAG.getMachineFunction().getSubtarget<ARMSubtarget>(); in EmitTargetCodeForMemcpy()
299 const ARMSubtarget &Subtarget = in EmitTargetCodeForMemset()
300 DAG.getMachineFunction().getSubtarget<ARMSubtarget>(); in EmitTargetCodeForMemset()
H A DThumb1InstrInfo.cpp26 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI) in Thumb1InstrInfo()
48 const ARMSubtarget &st = MF.getSubtarget<ARMSubtarget>(); in copyPhysReg()
174 const ARMSubtarget &ST = MF.getSubtarget<ARMSubtarget>(); in expandLoadStackGuard()
H A DARMInstrInfo.h20 class ARMSubtarget; variable
25 explicit ARMInstrInfo(const ARMSubtarget &STI);
H A DARMFrameLowering.h17 class ARMSubtarget; variable
23 const ARMSubtarget &STI;
26 explicit ARMFrameLowering(const ARMSubtarget &sti);
H A DARMTargetMachine.h39 mutable StringMap<std::unique_ptr<ARMSubtarget>> SubtargetMap;
49 const ARMSubtarget *getSubtargetImpl(const Function &F) const override;
53 const ARMSubtarget *getSubtargetImpl() const = delete;
H A DARMLegalizerInfo.h24 class ARMSubtarget; variable
28 ARMLegalizerInfo(const ARMSubtarget &ST);
H A DARMMacroFusion.cpp15 #include "ARMSubtarget.h"
55 const ARMSubtarget &ST = static_cast<const ARMSubtarget&>(TSI); in shouldScheduleAdjacent()
H A DThumb1FrameLowering.h16 class ARMSubtarget; variable
21 explicit Thumb1FrameLowering(const ARMSubtarget &sti);
H A DThumb1InstrInfo.h20 class ARMSubtarget; variable
25 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
H A DARMInstrInfo.cpp32 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI) : ARMBaseInstrInfo(STI) {} in ARMInstrInfo()
96 const ARMSubtarget &Subtarget = MF.getSubtarget<ARMSubtarget>(); in expandLoadStackGuard()
H A DARMMachineFunctionInfo.cpp30 const ARMSubtarget *Subtarget) { in GetBranchTargetEnforcement()
56 const ARMSubtarget *Subtarget) in ARMFunctionInfo()
H A DARM.h26 class ARMSubtarget; variable
53 createARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
H A DThumb2InstrInfo.h20 class ARMSubtarget; variable
25 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
H A DARMRegisterInfo.td237 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
254 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
266 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
277 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
287 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
300 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
308 return 1 + MF.getSubtarget<ARMSubtarget>().isThumb1Only();
334 return MF.getSubtarget<ARMSubtarget>().getGPRAllocationOrder(MF);
372 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
389 return MF.getSubtarget<ARMSubtarget>().isThumb1Only();
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H A DARMISelLowering.h37 class ARMSubtarget; variable
400 const ARMSubtarget &STI);
573 const ARMSubtarget* getSubtarget() const { in getSubtarget()
776 const ARMSubtarget *Subtarget;
818 const ARMSubtarget *Subtarget) const;
820 const ARMSubtarget *Subtarget) const;
852 const ARMSubtarget *ST) const;
854 const ARMSubtarget *ST) const;
862 const ARMSubtarget *Subtarget) const;
H A DARMBaseInstrInfo.h40 class ARMSubtarget; variable
43 const ARMSubtarget &Subtarget;
47 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
132 const ARMSubtarget &getSubtarget() const { return Subtarget; } in getSubtarget()
205 const ARMSubtarget &Subtarget) const;
208 const ARMSubtarget &Subtarget) const;
842 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
880 const ARMSubtarget *Subtarget,
887 const ARMSubtarget *Subtarget,
H A DARMSubtarget.h48 class ARMSubtarget : public ARMGenSubtargetInfo {
168 ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS,
190 ARMSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
H A DARMCallLowering.cpp167 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); in assignCustomValue()
226 auto const &ST = MIRBuilder.getMF().getSubtarget<ARMSubtarget>(); in lowerReturn()
345 bool IsLittle = MIRBuilder.getMF().getSubtarget<ARMSubtarget>().isLittle(); in assignCustomValue()
445 unsigned getCallOpcode(const MachineFunction &MF, const ARMSubtarget &STI, in getCallOpcode()
467 const auto &STI = MF.getSubtarget<ARMSubtarget>(); in lowerCall()
H A DARMMachineFunctionInfo.h30 class ARMSubtarget;
160 explicit ARMFunctionInfo(const Function &F, const ARMSubtarget *STI);
25 class ARMSubtarget; global() variable
H A DARMInstructionSelector.cpp35 ARMInstructionSelector(const ARMBaseTargetMachine &TM, const ARMSubtarget &STI,
77 const ARMSubtarget &STI;
82 const ARMSubtarget *Subtarget = &STI;
127 OpcodeCache(const ARMSubtarget &STI);
163 const ARMSubtarget &STI, in createARMInstructionSelector()
174 const ARMSubtarget &STI, in ARMInstructionSelector()
296 ARMInstructionSelector::OpcodeCache::OpcodeCache(const ARMSubtarget &STI) { in OpcodeCache()

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