Home
last modified time | relevance | path

Searched refs:ANY_EXTEND (Results 1 – 25 of 55) sorted by relevance

123

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h835 ANY_EXTEND, enumerator
1757 return Opcode == ISD::ANY_EXTEND || Opcode == ISD::ZERO_EXTEND || in isExtOpcode()
H A DSelectionDAG.h985 case ISD::ANY_EXTEND:
987 return ISD::ANY_EXTEND;
1001 case ISD::ANY_EXTEND:
1032 case ISD::ANY_EXTEND:
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp177 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; in PromoteIntegerResult()
398 case ISD::ANY_EXTEND: in PromoteIntRes_Atomic0()
461 case ISD::ANY_EXTEND: in PromoteIntRes_AtomicCmpSwap()
497 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
500 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp)); in PromoteIntRes_BITCAST()
513 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
530 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
571 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
600 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
623 return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res); in PromoteIntRes_BSWAP()
[all …]
H A DSelectionDAGBuilder.h323 ISD::NodeType ExtendType = ISD::ANY_EXTEND);
781 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
H A DLegalizeDAG.cpp3230 case ISD::ANY_EXTEND: in ExpandNode()
3356 Op = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, in ExpandNode()
3962 SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]); in ExpandNode()
4004 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) && in ExpandNode()
4010 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi); in ExpandNode()
4140 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); in ExpandNode()
5331 Tmp1 = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
5365 DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
5459 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
5514 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
[all …]
H A DLegalizeVectorTypes.cpp85 case ISD::ANY_EXTEND: in ScalarizeVectorResult()
520 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op); in ScalarizeVecRes_VecInregOp()
753 case ISD::ANY_EXTEND: in ScalarizeVectorOperand()
943 : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res); in ScalarizeVecOp_EXTRACT_VECTOR_ELT()
1071 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_VECREDUCE()
1281 case ISD::ANY_EXTEND: in SplitVectorResult()
2008 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec); in SplitVecRes_INSERT_VECTOR_ELT()
2011 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, EltVT, Elt); in SplitVecRes_INSERT_VECTOR_ELT()
3477 case ISD::ANY_EXTEND: in SplitVectorOperand()
3879 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec); in SplitVecOp_EXTRACT_VECTOR_ELT()
[all …]
H A DFunctionLoweringInfo.cpp65 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in getPreferredExtendForValue()
H A DDAGCombiner.cpp1517 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
1519 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op); in PromoteOperand()
1967 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); in visit()
2110 case ISD::ANY_EXTEND: in combine()
3978 Src = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Src); in foldSubCtlzNot()
6172 if ((HandOpcode == ISD::ANY_EXTEND || in hoistLogicOpWithSameOpcodeHands()
7158 if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse()) in combineShiftAnd1ToBitTest()
7460 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
8286 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NotHi); in visitORCommutative()
9052 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
[all …]
H A DLegalizeTypesGeneric.cpp226 OldVec = DAG.getNode(ISD::ANY_EXTEND, dl, NVecVT, N->getOperand(0)); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeTypes.cpp1006 Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi); in JoinIntegers()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp2796 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in lowerBITCAST()
3451 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(2))}); in lowerINTRINSIC_W_CHAIN()
3579 DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, in lowerINTRINSIC_VOID()
3594 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \ in lowerINTRINSIC_VOID()
3595 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3)) \ in lowerINTRINSIC_VOID()
3608 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, in lowerINTRINSIC_VOID()
3817 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp()
3852 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOpWithSExt()
3853 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOpWithSExt()
4034 ? ISD::ANY_EXTEND in ReplaceNodeResults()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h213 return ISD::ANY_EXTEND; in getExtendForAtomicOps()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp873 case ISD::ANY_EXTEND: in expandRxSBG()
993 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND && in tryRISBGZero()
1112 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND && in tryRxSBG()
2049 Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result); in expandSelectBoolean()
H A DSystemZISelLowering.h664 return ISD::ANY_EXTEND; in getExtendForAtomicOps()
H A DSystemZISelLowering.cpp1841 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
4072 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi); in lowerThreadPointer()
4309 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In); in lowerBITCAST()
4976 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op); in lowerCTPOP()
6218 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1); in joinDwords()
6220 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in joinDwords()
6222 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in joinDwords()
6223 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1); in joinDwords()
7290 SDValue In32 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src); in LowerOperationWrapper()
7294 SDValue In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Src); in LowerOperationWrapper()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp240 setOperationAction(ISD::ANY_EXTEND, T, Custom); in initializeHVXLowering()
283 setOperationAction(ISD::ANY_EXTEND, T, Custom); in initializeHVXLowering()
432 setOperationAction(ISD::ANY_EXTEND, VecTy, Custom); in initializeHVXLowering()
1671 SDValue ToInt32 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, ToInt16); in LowerHvxSplatVector()
2938 case ISD::ANY_EXTEND: in CreateTLWrapper()
3248 case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG); in LowerHvxOperation()
3303 case ISD::ANY_EXTEND: in ExpandHvxResizeIntoSteps()
3404 case ISD::ANY_EXTEND: in LowerHvxOperationWrapper()
3470 case ISD::ANY_EXTEND: in ReplaceHvxNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp715 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, ValLoc, ValToCopy); in lowerMasksToReg()
726 return DAG.getNode(ISD::ANY_EXTEND, DL, ValLoc, ValArg); in lowerMasksToReg()
797 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2229 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); in LowerCall()
2695 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST || in MatchingStackOffset()
H A DX86ISelDAGToDAG.cpp1226 case ISD::ANY_EXTEND: in PreprocessISelDAG()
1235 assert(N->getOpcode() == ISD::ANY_EXTEND && in PreprocessISelDAG()
1239 NewOpc = N->getOpcode() == ISD::ANY_EXTEND in PreprocessISelDAG()
2159 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in foldMaskedShiftToScaledMask()
2186 SDValue NewX = DAG.getNode(ISD::ANY_EXTEND, DL, VT, X); in foldMaskedShiftToScaledMask()
2276 if (X.getOpcode() == ISD::ANY_EXTEND) { in foldMaskAndShiftToScale()
2698 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || in matchAddressRecursively()
4079 NBits = CurDAG->getNode(ISD::ANY_EXTEND, DL, NVT, NBits); in matchBitExtract()
4137 Control = CurDAG->getNode(ISD::ANY_EXTEND, DL, XVT, Control); in matchBitExtract()
4494 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in tryShrinkShlLogicImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp141 SrcOrValue = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, SrcOrValue); in EmitMOPS()
H A DAArch64ISelLowering.cpp1142 setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND, in AArch64TargetLowering()
1374 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal); in AArch64TargetLowering()
2275 setOperationAction(ISD::ANY_EXTEND, VT, Default); in addTypeForFixedLengthSVE()
5130 DAG.getNode(ISD::ANY_EXTEND, SDLoc(Op), getSVEContainerType(ArgVT), in LowerBITCAST()
5156 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0)); in LowerBITCAST()
5215 N.getOpcode() == ISD::ANY_EXTEND || in isSignExtended()
5221 N.getOpcode() == ISD::ANY_EXTEND || in isZeroExtended()
6203 Scalar = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Scalar); in LowerINTRINSIC_WO_CHAIN()
6636 StoreVal = DAG.getNode(ISD::ANY_EXTEND, DL, PromotedVT, StoreVal); in LowerMSCATTER()
6976 Vec = DAG.getNode(ISD::ANY_EXTEND, DL, ContainerVT, Vec); in LowerVECTOR_COMPRESS()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp308 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) { in MatchingStackOffset()
665 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
1109 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1661 Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src); in getBitTestCondition()
1666 BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo); in getBitTestCondition()
3545 Carry.getOpcode() == ISD::ANY_EXTEND || in combineCarryThroughADD()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp883 setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, in RISCVTargetLowering()
1375 {ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, VT, Custom); in RISCVTargetLowering()
3900 LastOp = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, LastOp); in lowerBuildVectorViaDominantValues()
4027 Splat = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Splat); in lowerBuildVectorOfConstants()
4334 Splat = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Splat); in lowerBUILD_VECTOR()
4343 Splat = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Splat); in lowerBUILD_VECTOR()
4507 V = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), V); in lowerBUILD_VECTOR()
4613 isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; in lowerScalarSplat()
4677 isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; in lowerScalarInsert()
5098 Splat = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), Splat); in lowerVECTOR_SHUFFLEAsVSlide1()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp724 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1117 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), in LowerSIGN_EXTEND()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp750 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
754 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
757 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
3334 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn()
3942 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
6793 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS); in ReplaceNodeResults()
6794 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS); in ReplaceNodeResults()
7210 return ISD::ANY_EXTEND; in getExtOpcodeForPromotedOp()
8080 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo); in lowerBUILD_VECTOR()
8449 Addr = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Addr); in packImage16bitOpsToDwords()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DTargetLoweringBase.cpp1747 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in GetReturnInfo()
1754 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) in GetReturnInfo()

123