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Searched refs:ANY_EXTEND (Results 1 – 25 of 55) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h811 ANY_EXTEND, enumerator
1646 return Opcode == ISD::ANY_EXTEND || Opcode == ISD::ZERO_EXTEND || in isExtOpcode()
H A DSelectionDAG.h922 case ISD::ANY_EXTEND:
924 return ISD::ANY_EXTEND;
938 case ISD::ANY_EXTEND:
969 case ISD::ANY_EXTEND:
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeIntegerTypes.cpp159 case ISD::ANY_EXTEND: Res = PromoteIntRes_INT_EXTEND(N); break; in PromoteIntegerResult()
383 case ISD::ANY_EXTEND: in PromoteIntRes_Atomic0()
444 case ISD::ANY_EXTEND: in PromoteIntRes_AtomicCmpSwap()
480 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); in PromoteIntRes_BITCAST()
483 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftPromotedHalf(InOp)); in PromoteIntRes_BITCAST()
496 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
513 InOp = DAG.getNode(ISD::ANY_EXTEND, dl, in PromoteIntRes_BITCAST()
554 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, InOp); in PromoteIntRes_BITCAST()
560 return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, in PromoteIntRes_BITCAST()
583 return DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Res); in PromoteIntRes_BSWAP()
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H A DSelectionDAGBuilder.h324 ISD::NodeType ExtendType = ISD::ANY_EXTEND);
784 ISD::NodeType PreferredExtendType = ISD::ANY_EXTEND) const;
H A DLegalizeDAG.cpp3200 case ISD::ANY_EXTEND: in ExpandNode()
3325 Op = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, in ExpandNode()
3823 SDValue Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Halves[2 * i + 1]); in ExpandNode()
3865 TLI.isOperationLegalOrCustom(ISD::ANY_EXTEND, VT) && in ExpandNode()
3871 Hi = DAG.getNode(ISD::ANY_EXTEND, dl, VT, Hi); in ExpandNode()
4001 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); in ExpandNode()
5121 Tmp1 = DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
5154 DAG.getNode(ISD::ANY_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
5248 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
5303 ExtOp = ISD::ANY_EXTEND; in PromoteNode()
[all …]
H A DFunctionLoweringInfo.cpp65 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; in getPreferredExtendForValue()
H A DLegalizeVectorTypes.cpp83 case ISD::ANY_EXTEND: in ScalarizeVectorResult()
514 return DAG.getNode(ISD::ANY_EXTEND, DL, EltVT, Op); in ScalarizeVecRes_VecInregOp()
749 case ISD::ANY_EXTEND: in ScalarizeVectorOperand()
895 : DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res);
1024 Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Res); in ScalarizeVecOp_VECREDUCE_SEQ()
1227 case ISD::ANY_EXTEND: in SplitVectorResult()
1933 Vec = DAG.getNode(ISD::ANY_EXTEND, dl, VecVT, Vec); in SplitVecRes_INSERT_VECTOR_ELT()
1936 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, EltVT, Elt); in SplitVecRes_INSERT_VECTOR_ELT()
3202 case ISD::ANY_EXTEND: in SplitVectorOperand()
3569 Vec = DAG.getNode(ISD::ANY_EXTEND, d in SplitVecOp_EXTRACT_VECTOR_ELT()
[all...]
H A DDAGCombiner.cpp1460 if (!TLI.isOperationLegal(ISD::ANY_EXTEND, PVT)) in PromoteOperand()
1462 return DAG.getNode(ISD::ANY_EXTEND, DL, PVT, Op); in PromoteOperand()
1909 case ISD::ANY_EXTEND: return visitANY_EXTEND(N); in visit()
2041 case ISD::ANY_EXTEND: in combine()
5797 if ((HandOpcode == ISD::ANY_EXTEND || in hoistLogicOpWithSameOpcodeHands()
6766 if (And0.getOpcode() == ISD::ANY_EXTEND && And0.hasOneUse()) in combineShiftAnd1ToBitTest()
7038 if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) { in visitAND()
7826 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NotHi); in visitORCommutative()
8594 LHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
8598 RHSShiftAmt.getOpcode() == ISD::ANY_EXTEND || in MatchRotate()
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H A DLegalizeTypesGeneric.cpp226 OldVec = DAG.getNode(ISD::ANY_EXTEND, dl, NVecVT, N->getOperand(0)); in ExpandRes_EXTRACT_VECTOR_ELT()
H A DLegalizeTypes.cpp1003 Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi); in JoinIntegers()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp1647 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in lowerBITCAST()
2288 {Chain, DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(2))}); in lowerINTRINSIC_W_CHAIN()
2416 DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, in lowerINTRINSIC_VOID()
2431 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \ in lowerINTRINSIC_VOID()
2432 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3)) \ in lowerINTRINSIC_VOID()
2445 DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, in lowerINTRINSIC_VOID()
2648 unsigned ExtOpc = ISD::ANY_EXTEND) { in customLegalizeToWOp()
2683 SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(0)); in customLegalizeToWOpWithSExt()
2684 SDValue NewOp1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1)); in customLegalizeToWOpWithSExt()
2892 SDValue NewSrc = DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Src); in ReplaceNodeResults()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.h212 return ISD::ANY_EXTEND;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp835 setOperationAction({ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, in RISCVTargetLowering()
1256 {ISD::ANY_EXTEND, ISD::SIGN_EXTEND, ISD::ZERO_EXTEND}, VT, Custom); in RISCVTargetLowering()
3585 LastOp = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, LastOp); in lowerBuildVectorViaDominantValues()
3714 Splat = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Splat); in lowerBuildVectorOfConstants()
4061 Splat = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Splat); in lowerBUILD_VECTOR()
4226 V = DAG.getNode(ISD::ANY_EXTEND, DL, Subtarget.getXLenVT(), V); in lowerBUILD_VECTOR()
4320 // of being able to use a .vi instruction. ANY_EXTEND would become a in lowerScalarSplat()
4324 isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; in lowerScalarSplat()
4387 // of being able to use a .vi instruction. ANY_EXTEND would become a in lowerScalarInsert()
4391 isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND; in lowerScalarInsert()
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SelectionDAGInfo.cpp66 SrcOrValue = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, SrcOrValue); in EmitMOPS()
H A DAArch64ISelLowering.cpp1100 setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND, in AArch64TargetLowering()
1319 setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal); in AArch64TargetLowering()
2039 setOperationAction(ISD::ANY_EXTEND, VT, Default); in addTypeForFixedLengthSVE()
4927 DAG.getNode(ISD::ANY_EXTEND, SDLoc(Op), getSVEContainerType(ArgVT), in LowerBITCAST()
4944 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op.getOperand(0)); in LowerBITCAST()
5057 N.getOpcode() == ISD::ANY_EXTEND || in isSignExtended()
5063 N.getOpcode() == ISD::ANY_EXTEND || in isZeroExtended()
5899 Scalar = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Scalar); in LowerINTRINSIC_WO_CHAIN()
6341 StoreVal = DAG.getNode(ISD::ANY_EXTEND, DL, PromotedVT, StoreVal); in LowerMSCATTER()
6972 case ISD::ANY_EXTEND: in LowerOperation()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelDAGToDAG.cpp873 case ISD::ANY_EXTEND: in expandRxSBG()
993 if (RISBG.Input.getOpcode() != ISD::ANY_EXTEND && in tryRISBGZero()
1102 if (RxSBG[I].Input.getOpcode() != ISD::ANY_EXTEND && in tryRxSBG()
2037 Result = CurDAG->getNode(ISD::ANY_EXTEND, DL, VT, Result); in expandSelectBoolean()
H A DSystemZISelLowering.h641 return ISD::ANY_EXTEND; in getExtendForAtomicOps()
H A DSystemZISelLowering.cpp1513 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
3616 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi); in lowerThreadPointer()
3856 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In); in lowerBITCAST()
4501 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op); in lowerCTPOP()
5613 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1); in joinDwords()
5615 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in joinDwords()
5617 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0); in joinDwords()
5618 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1); in joinDwords()
6726 if (N0.hasOneUse() && N0.getOpcode() == ISD::ANY_EXTEND) in combineSIGN_EXTEND_INREG()
6755 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT, in combineSIGN_EXTEND()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp236 setOperationAction(ISD::ANY_EXTEND, T, Custom); in initializeHVXLowering()
279 setOperationAction(ISD::ANY_EXTEND, T, Custom); in initializeHVXLowering()
422 setOperationAction(ISD::ANY_EXTEND, VecTy, Custom); in initializeHVXLowering()
1655 SDValue ToInt32 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, ToInt16); in LowerHvxSplatVector()
2901 case ISD::ANY_EXTEND: in CreateTLWrapper()
3211 case ISD::ANY_EXTEND: return LowerHvxAnyExt(Op, DAG); in LowerHvxOperation()
3266 case ISD::ANY_EXTEND: in ExpandHvxResizeIntoSteps()
3367 case ISD::ANY_EXTEND: in LowerHvxOperationWrapper()
3433 case ISD::ANY_EXTEND: in ReplaceHvxNodeResults()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp697 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, ValLoc, ValToCopy); in lowerMasksToReg()
708 return DAG.getNode(ISD::ANY_EXTEND, DL, ValLoc, ValArg); in lowerMasksToReg()
779 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
2186 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); in LowerCall()
2640 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST || in MatchingStackOffset()
H A DX86ISelDAGToDAG.cpp1182 case ISD::ANY_EXTEND: in PreprocessISelDAG()
1191 assert(N->getOpcode() == ISD::ANY_EXTEND && in PreprocessISelDAG()
1195 NewOpc = N->getOpcode() == ISD::ANY_EXTEND in PreprocessISelDAG()
2101 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in foldMaskedShiftToScaledMask()
2128 SDValue NewX = DAG.getNode(ISD::ANY_EXTEND, DL, VT, X); in foldMaskedShiftToScaledMask()
2218 if (X.getOpcode() == ISD::ANY_EXTEND) { in foldMaskAndShiftToScale()
2641 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || in matchAddressRecursively()
4013 NBits = CurDAG->getNode(ISD::ANY_EXTEND, DL, NVT, NBits); in matchBitExtract()
4071 Control = CurDAG->getNode(ISD::ANY_EXTEND, DL, XVT, Control); in matchBitExtract()
4428 if (Shift.getOpcode() == ISD::ANY_EXTEND && Shift.hasOneUse() && in tryShrinkShlLogicImm()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp306 if (Op == ISD::ZERO_EXTEND || Op == ISD::ANY_EXTEND || Op == ISD::BITCAST) { in MatchingStackOffset()
663 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, RegVT, Arg); in LowerCall()
1107 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1659 Src = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Src); in getBitTestCondition()
1664 BitNo = DAG.getNode(ISD::ANY_EXTEND, DL, Src.getValueType(), BitNo); in getBitTestCondition()
3545 Carry.getOpcode() == ISD::ANY_EXTEND || in combineCarryThroughADD()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp734 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
738 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
741 setOperationAction({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND}, in SITargetLowering()
3214 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerReturn()
3773 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCall()
6424 LHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, LHS); in ReplaceNodeResults()
6425 RHS = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, RHS); in ReplaceNodeResults()
7532 SDValue ExtLo = DAG.getNode(ISD::ANY_EXTEND, SL, MVT::i32, Lo); in lowerBUILD_VECTOR()
7886 Addr = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Addr); in packImage16bitOpsToDwords()
10143 SDValue BufferStoreExt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Ops[1]); in handleByteShortBufferStores()
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/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp844 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1239 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Val), in LowerSIGN_EXTEND()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1816 StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal); in LowerCall()
2889 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1); in LowerSelect()
2890 Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2); in LowerSelect()
3071 ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal); in LowerSTOREVector()
3451 RetVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, RetVal); in LowerReturn()
5526 if (Val.getOpcode() == ISD::ANY_EXTEND) { in PerformANDCombine()
5936 Result = DCI.DAG.getNode(ISD::ANY_EXTEND, DL, N->getValueType(0), Result); in PerformEXTRACTCombine()

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