| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMScheduleR52.td | 308 def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "AD(C|D)S?ri", "ANDS?ri",
314 "ANDS?rr", "BICS?rr", "CRC", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr",
318 "ANDS?rsi", "BICS?rsi", "EORrsi", "ORRrsi", "RSBrsi", "RSCrsi", "SBCrsi",
322 (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr",
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64SchedOryon.td | 741 //1,1,4 TST is an alias of ANDS
743 (instregex "^ANDS(W|X)r(i|r|x)", "^BICS(W|X)r(i|r|x)")>;
747 (instregex "^ANDS(W|X)rs", "^BICS(W|X)rs")>;
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| H A D | AArch64SchedA64FX.td | 603 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
623 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
640 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
2093 (instregex "^ANDS?_P", "^BICS?_P", "^BRK.*_P", "^EORS?_P", "^ORRS?_P",
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| H A D | AArch64SchedThunderX2T99.td | 427 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
449 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
468 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
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| H A D | AArch64SchedThunderX3T110.td | 687 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
709 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
728 "AND?(W|X)r(i|r|s|x)", "ANDS?(W|X)r(i|r|s|x)",
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| H A D | AArch64SchedTSV110.td | 58 // 1cyc_1BRU: ADDS, ADCS, ANDS, BICS, SUBS, SBCS, CCMN, CCMP
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| H A D | AArch64SchedNeoverseV2.td | 1121 "^ANDS[WX]ri$",
2073 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;
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| H A D | AArch64SchedA510.td | 602 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;
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| H A D | AArch64SchedA320.td | 624 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;
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| H A D | AArch64SchedNeoverseV1.td | 602 "^ANDS[WX]ri$",
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| H A D | AArch64SchedNeoverseN2.td | 1588 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP$")>;
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| H A D | AArch64SchedNeoverseN3.td | 1558 (instregex "^(ANDS|BICS|EORS|NANDS|NORS|ORNS|ORRS)_PPzPP")>;
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| H A D | AArch64ISelLowering.cpp | 3483 DAG.getNode(AArch64ISD::ANDS, DL, DAG.getVTList(VT, MVT_CC), in emitComparison()
3488 } else if (LHS.getOpcode() == AArch64ISD::ANDS) { in emitComparison()
3834 if (LHS.getOpcode() != ISD::AND && LHS.getOpcode() != AArch64ISD::ANDS) in shouldBeAdjustedToZero()
4039 DAG.getNode(AArch64ISD::ANDS, DL, VTs, Mul, UpperBits).getValue(1); in getAArch64XALUOOp()
24686 SDValue ANDS = DAG.getNode( in performSubsToAndsCombine() local
24687 AArch64ISD::ANDS, DL, SubsNode->getVTList(), AndNode->getOperand(0), in performSubsToAndsCombine()
24702 ANDS.getValue(1)}; in performSubsToAndsCombine()
26742 case AArch64ISD::ANDS: in PerformDAGCombine()
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| H A D | AArch64ISelDAGToDAG.cpp | 3930 !isOpcWithIntImmediate(ShiftAmt.getNode(), AArch64ISD::ANDS, MaskImm)) in tryShiftAmountMod()
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| H A D | AArch64InstrInfo.td | 839 def AArch64and_flag : SDNode<"AArch64ISD::ANDS", SDTBinaryArithWithFlagsOut,
3113 defm ANDS : LogicalImmS<0b11, "ands", AArch64and_flag, "bics">;
3128 defm ANDS : LogicalRegS<0b11, 0, "ands", AArch64and_flag>;
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