| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsMachineFunction.cpp | 126 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
153 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg) in initGlobalBaseReg()
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| H A D | MipsInstructionSelector.cpp | 343 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select()
376 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select() local
380 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select()
397 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu)) in select() local
402 if (!constrainSelectedInstRegOperands(*ADDu, TII, TRI, RBI)) in select()
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| H A D | MipsExpandPseudo.cpp | 364 Opcode = Mips::ADDu; in expandAtomicBinOpSubword()
780 Opcode = Mips::ADDu; in expandAtomicBinOp()
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| H A D | MicroMipsSizeReduction.cpp | 222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
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| H A D | MipsBranchExpansion.cpp | 515 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT) in expandToLongBranch()
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| H A D | MipsScheduleI6400.td | 110 (instrs ADD, ADDiu, ADDIUPC, ADDu, ALIGN, ALUIPC, AND, ANDi, AUI,
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| H A D | MipsScheduleP5600.td | 226 ADDu, SLLV, SRAV, SRLV, LSA, COPY)>;
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| H A D | MipsInstrInfo.td | 2065 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
2693 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
3160 (ADDu GPR32:$lhs, GPR32:$rhs)>, ISA_MIPS1, ASE_NOT_DSP;
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| H A D | MipsFastISel.cpp | 2125 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg()); in simplifyAddress()
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| H A D | MipsScheduleGeneric.td | 47 def : InstRW<[GenericWriteALU], (instrs ADD, ADDi, ADDiu, ADDu, AND, ANDi,
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| H A D | Mips64InstrInfo.td | 919 (ADDu GPR32:$src, GPR32:$src2), sub_32)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsABIInfo.cpp | 102 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu; in GetPtrAdduOp()
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| H A D | MipsTargetStreamer.cpp | 281 emitRRR(Is64Bit ? Mips::DADDu : Mips::ADDu, DstReg, SrcReg, TrgReg, SMLoc(), in emitAddu()
354 emitRRR(Mips::ADDu, ATReg, ATReg, BaseReg, IDLoc, STI); in emitStoreWithImmOffset()
389 emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in emitLoadWithImmOffset()
1283 TmpInst.setOpcode(Mips::ADDu); in emitDirectiveCpLoad()
1356 emitRRR(Mips::ADDu, GPReg, GPReg, RegNo, SMLoc(), &STI); in emitDirectiveCpsetup()
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| H A D | MipsInstPrinter.cpp | 331 case Mips::ADDu: in printAlias()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 2739 unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu; in loadImmediate()
2973 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg, in loadAndAddSymbolAddress()
3018 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg, in loadAndAddSymbolAddress()
3030 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3094 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg, in loadAndAddSymbolAddress()
3234 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI); in loadAndAddSymbolAddress()
3748 TOut.emitRRR(ABI.ArePtrs64bit() ? Mips::DADDu : Mips::ADDu, TmpReg, in expandMem16Inst()
3806 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI); in expandMem16Inst()
4799 FinalOpcode = Mips::ADDu; in expandAliasImmediate()
5159 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI); in expandAbs()
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