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Searched refs:ADDI (Results 1 – 25 of 59) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVMatInt.cpp33 case RISCV::ADDI: in getInstSeqCost()
97 unsigned AddiOpc = RISCV::ADDI; in generateInstSeqImpl()
185 Res.emplace_back(RISCV::ADDI, Lo12); in generateInstSeqImpl()
304 TmpSeq.emplace_back(RISCV::ADDI, Imm12); in generateInstSeq()
366 if (Res[0].getOpcode() == RISCV::ADDI && Res[0].getImm() == 1 && in generateInstSeq()
442 TmpSeq.emplace_back(RISCV::ADDI, Lo12); in generateInstSeq()
457 TmpSeq.emplace_back(RISCV::ADDI, NegImm12); in generateInstSeq()
572 case RISCV::ADDI: in getOpndKind()
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVCInstructions.h166 return ADDI{rd, Rs{0}, uint32_t(imm)}; in DecodeC_LI()
167 return ADDI{rd, Rs{0}, uint32_t(int32_t(int8_t(imm | 0xc0)))}; in DecodeC_LI()
183 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, uint32_t(nzimm)}; in DecodeC_LUI_ADDI16SP()
184 return ADDI{Rd{gpr_sp_riscv}, Rs{gpr_sp_riscv}, in DecodeC_LUI_ADDI16SP()
200 return ADDI{rd, rd, uint32_t(imm)}; in DecodeC_ADDI()
201 return ADDI{rd, rd, uint32_t(int32_t(int8_t(imm | 0xc0)))}; in DecodeC_ADDI()
225 return ADDI{rd, Rs{gpr_sp_riscv}, uint32_t(nzuimm)}; in DecodeC_ADDI4SPN()
H A DRISCVInstructions.h121 I_TYPE_INST(ADDI);
276 LUI, AUIPC, JAL, JALR, B, LB, LH, LW, LBU, LHU, SB, SH, SW, ADDI, SLTI,
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp110 if (Lo->getOpcode() != RISCV::ADDI) in INITIALIZE_PASS()
207 if (OffsetTail.getOpcode() == RISCV::ADDI || in foldLargeOffset()
291 if (OffsetTail.getOpcode() != RISCV::ADDI) in foldShiftedOffset()
335 case RISCV::ADDI: { in detectAndFoldOffset()
343 if (TailTail.getOpcode() == RISCV::ADDI) { in detectAndFoldOffset()
H A DRISCVOptWInstrs.cpp313 case RISCV::ADDI: in hasAllNBitUsers()
387 case RISCV::ADDI: in isSignExtendingOpW()
606 case RISCV::ADDI: { in isSignExtendedW()
654 case RISCV::ADDI: in getWOp()
736 case RISCV::ADDIW: Opc = RISCV::ADDI; break; in stripWSuffixes()
766 case RISCV::ADDI: in appendWSuffixes()
H A DRISCVRegisterInfo.cpp300 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
342 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
346 BuildMI(MBB, II, DL, TII->get(RISCV::ADDI), DestReg) in adjustReg()
579 if (Opc == RISCV::ADDI && !isInt<12>(Val)) { in eliminateFrameIndex()
610 if (MI.getOpcode() == RISCV::ADDI) in eliminateFrameIndex()
626 if (MI.getOpcode() == RISCV::ADDI && in eliminateFrameIndex()
763 BuildMI(*MBB, MBBI, DL, TII->get(RISCV::ADDI), BaseReg) in materializeFrameBaseRegister()
966 case RISCV::ADDI: in getRegAllocationHints()
1025 if ((MI.getOpcode() == RISCV::ADDIW || MI.getOpcode() == RISCV::ADDI) && in getRegAllocationHints()
H A DRISCVExpandPseudoInsts.cpp210 BuildMI(TrueBB, DL, TII->get(RISCV::ADDI), DestReg) in expandCCOp()
226 case RISCV::PseudoCCADDI: NewOpc = RISCV::ADDI; break; in expandCCOp()
302 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg) in expandMV_FPR16INX()
319 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DstReg) in expandMV_FPR32INX()
597 RISCV::ADDI); in expandLoadLocalAddress()
620 RISCV::ADDI); in expandLoadTLSGDAddress()
651 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), RISCV::X10) in expandLoadTLSDescAddress()
H A DRISCVAsmPrinter.cpp536 EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::ADDI) in emitSled()
666 EmitToStreamer(*OutStreamer, MCInstBuilder(RISCV::ADDI) in LowerKCFI_CHECK()
701 : RISCV::ADDI) in LowerKCFI_CHECK()
809 MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
830 MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
896 MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
932 MCInstBuilder(RISCV::ADDI).addReg(RISCV::X10).addReg(Reg).addImm(0), in EmitHwasanMemaccessSymbols()
935 MCInstBuilder(RISCV::ADDI) in EmitHwasanMemaccessSymbols()
H A DRISCVMacroFusion.cpp
H A DRISCVInstrInfo.cpp93 return MCInstBuilder(RISCV::ADDI) in getNop()
519 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg) in copyPhysReg()
546 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), in copyPhysReg()
550 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), in copyPhysReg()
1445 if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() && in isLoadImm()
1657 case RISCV::ADDI: return RISCV::PseudoCCADDI; break; in getPredicatedOpcode()
1703 if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(1).isReg() && in canFoldAsPredicatedOp()
1918 case RISCV::ADDI: in isAsCheapAsAMove()
1945 case RISCV::ADDI: in isCopyInstrImpl()
3080 if (AddrI.getOpcode() != RISCV::ADDI || !AddrI.getOperand(1).isReg() || in canFoldIntoAddrMode()
[all …]
H A DRISCVInstrInfo.td133 // Add the Lo 12 bits from an address. Selected to ADDI.
139 // Represents an AUIPC+ADDI pair. Selected to PseudoLLA.
542 // Check if (add r, imm) can be optimized to (ADDI (ADDI r, imm0), imm1),
768 // ADDI isn't always rematerializable, but isReMaterializable will be used as
771 def ADDI : ALU_ri<0b000, "addi">;
1029 def : InstAlias<"nop", (ADDI X0, X0, 0), 3>;
1030 def : InstAlias<"li $rd, $imm", (ADDI GPR:$rd, X0, simm12:$imm), 2>;
1031 def : InstAlias<"mv $rd, $rs", (ADDI GPR:$rd, GPR:$rs, 0)>;
1167 (ADDI GPR:$rd, GPR:$rs1, simm12:$imm12)>;
1439 def : PatGprSimm12<add, ADDI>;
[all …]
H A DRISCVPostRAExpandPseudoInsts.cpp112 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI)) in expandMovAddr()
H A DRISCVInstrPredicates.td144 CheckOpcode<[ADDI]>,
H A DRISCVGISel.td58 (SLTIU (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm12)), 1)>;
63 (SLTU (XLenVT X0), (ADDI GPR:$rs1, (NegImm simm12Plus1:$imm12)))>;
H A DRISCVInstrInfoC.td852 def : CompressPat<(ADDI GPRC:$rd, SP:$rs1, uimm10_lsb00nonzero:$imm),
906 def : CompressPat<(ADDI X0, X0, 0), (C_NOP)>;
907 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs1, simm6nonzero:$imm),
922 def : CompressPat<(ADDI GPRNoX0:$rd, X0, simm6:$imm),
924 def : CompressPat<(ADDI X2, X2, simm10_lsb0000nonzero:$imm),
1020 def : CompressPat<(ADDI GPRNoX0:$rs1, GPRNoX0:$rs2, 0),
H A DRISCVFoldMemOffset.cpp249 if (MI.getOpcode() != RISCV::ADDI) in runOnMachineFunction()
H A DRISCVMakeCompressible.cpp441 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(RISCV::ADDI), NewReg) in runOnMachineFunction()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCMacroFusion.def35 FUSION_OP_SET(ADDI, ADDI8, ADDItocL, ADDItocL8), \
138 FUSION_OP_SET(ADDI, ADDI8, ADDItocL8, ADDItocL))
142 FUSION_OP_SET(ADDI, ADDI8, ADDItocL8, ADDItocL),
H A DPPCBack2BackFusion.def21 ADDI,
510 ADDI,
H A DPPCMachineScheduler.cpp25 return Cand.SU->getInstr()->getOpcode() == PPC::ADDI || in isADDIInstr()
H A DPPCCTRLoops.cpp247 unsigned ADDIOpcode = Is64Bit ? PPC::ADDI8 : PPC::ADDI; in expandNormalLoops()
H A DPPCRegisterInfo.cpp108 ImmToIdxMap[PPC::ADDI] = PPC::ADD4; in PPCRegisterInfo()
782 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg()) in lowerDynamicAlloc()
835 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), FramePointer) in prepareDynamicAlloca()
1983 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) && in needsFrameBaseReg()
2013 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI; in materializeFrameBaseRegister()
/freebsd/contrib/llvm-project/lld/ELF/Arch/
H A DRISCV.cpp64 ADDI = 0x13, enumerator
238 write32le(buf + 12, itype(ADDI, X_T1, X_T1, -ctx.target->pltHeaderSize - 12)); in writePltHeader()
239 write32le(buf + 16, itype(ADDI, X_T0, X_T2, lo12(offset))); in writePltHeader()
255 write32le(buf + 12, itype(ADDI, 0, 0, 0)); in writePlt()
583 write32le(loc, itype(ADDI, X_A0, 0, val)); // addi a0,zero,<lo12> in tlsdescToLe()
585 write32le(loc, itype(ADDI, X_A0, X_A0, lo12(val))); // addi a0,a0,<lo12> in tlsdescToLe()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp984 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressPcrel() local
988 Insts.push_back(LoongArchAsmParser::Inst(ADDI, ELF::R_LARCH_PCALA_LO12)); in emitLoadAddressPcrel()
1194 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressTLSLD() local
1227 Insts.push_back(LoongArchAsmParser::Inst(ADDI, ELF::R_LARCH_GOT_PC_LO12)); in emitLoadAddressTLSLD()
1266 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressTLSGD() local
1299 Insts.push_back(LoongArchAsmParser::Inst(ADDI, ELF::R_LARCH_GOT_PC_LO12)); in emitLoadAddressTLSGD()
1337 unsigned ADDI = is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W; in emitLoadAddressTLSDesc() local
1384 LoongArchAsmParser::Inst(ADDI, ELF::R_LARCH_TLS_DESC_PC_LO12)); in emitLoadAddressTLSDesc()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchInstrInfo.cpp644 MachineInstr &ADDI = in insertIndirectBranch() local
672 ADDI.getOperand(2).setMBB(&RestoreBB); in insertIndirectBranch()

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