| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64MachineScheduler.cpp | 29 return AArch64InstrInfo::getLdStOffsetOp(*MI).isImm(); in needReorderStoreMI()
38 const MachineOperand &Base0 = AArch64InstrInfo::getLdStBaseOp(MI0); in mayOverlapWrite()
39 const MachineOperand &Base1 = AArch64InstrInfo::getLdStBaseOp(MI1); in mayOverlapWrite()
45 int StoreSize0 = AArch64InstrInfo::getMemScale(MI0); in mayOverlapWrite()
46 int StoreSize1 = AArch64InstrInfo::getMemScale(MI1); in mayOverlapWrite()
47 Off0 = AArch64InstrInfo::hasUnscaledLdStOffset(MI0.getOpcode()) in mayOverlapWrite()
48 ? AArch64InstrInfo::getLdStOffsetOp(MI0).getImm() in mayOverlapWrite()
49 : AArch64InstrInfo::getLdStOffsetOp(MI0).getImm() * StoreSize0; in mayOverlapWrite()
50 Off1 = AArch64InstrInfo::hasUnscaledLdStOffset(MI1.getOpcode()) in mayOverlapWrite()
51 ? AArch64InstrInfo::getLdStOffsetOp(MI1).getImm() in mayOverlapWrite()
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| H A D | AArch64MacroFusion.cpp | 64 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticBccPair()
114 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticCbzPair()
251 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isCCSelectPair()
253 return !AArch64InstrInfo::hasExtendedReg(*FirstMI); in isCCSelectPair()
269 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isCCSelectPair()
272 return !AArch64InstrInfo::hasExtendedReg(*FirstMI); in isCCSelectPair()
285 if (AArch64InstrInfo::hasShiftedReg(SecondMI)) in isArithmeticLogicPair()
346 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticLogicPair()
374 return !AArch64InstrInfo::hasShiftedReg(*FirstMI); in isArithmeticLogicPair()
414 if (AArch64InstrInfo::hasShiftedReg(*FirstMI)) in isAddSub2RegAndConstOnePair()
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| H A D | AArch64LoadStoreOptimizer.cpp | 130 const AArch64InstrInfo *TII;
667 bool IsPaired = AArch64InstrInfo::isPairedLdSt(MI); in getPrePostIndexedMemOpInfo()
672 Scale = (IsTagStore || IsPaired) ? AArch64InstrInfo::getMemScale(MI) : 1; in getPrePostIndexedMemOpInfo()
686 bool IsPreLdSt = AArch64InstrInfo::isPreLdSt(MI); in getLdStRegOp()
690 AArch64InstrInfo::isPairedLdSt(MI) || IsPreLdSt ? PairedRegOp : 0; in getLdStRegOp()
696 const AArch64InstrInfo *TII) { in isLdOffsetInRangeOfSt()
702 ? AArch64InstrInfo::getLdStOffsetOp(StoreInst).getImm() in isLdOffsetInRangeOfSt()
703 : AArch64InstrInfo::getLdStOffsetOp(StoreInst).getImm() * StoreSize; in isLdOffsetInRangeOfSt()
706 ? AArch64InstrInfo::getLdStOffsetOp(LoadInst).getImm() in isLdOffsetInRangeOfSt()
707 : AArch64InstrInfo::getLdStOffsetOp(LoadInst).getImm() * LoadSize; in isLdOffsetInRangeOfSt()
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| H A D | AArch64InstrInfo.cpp | 86 AArch64InstrInfo::AArch64InstrInfo(const AArch64Subtarget &STI) in AArch64InstrInfo() function in AArch64InstrInfo
93 unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { in getInstSizeInBytes()
186 unsigned AArch64InstrInfo::getInstBundleLength(const MachineInstr &MI) const { in getInstBundleLength()
266 bool AArch64InstrInfo::isBranchOffsetInRange(unsigned BranchOp, in isBranchOffsetInRange()
275 AArch64InstrInfo::getBranchDestBlock(const MachineInstr &MI) const { in getBranchDestBlock()
300 void AArch64InstrInfo::insertIndirectBranch(MachineBasicBlock &MBB, in insertIndirectBranch()
373 bool AArch64InstrInfo::analyzeBranch(MachineBasicBlock &MBB, in analyzeBranch()
489 bool AArch64InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB, in analyzeBranchPredicate()
539 bool AArch64InstrInfo::reverseBranchCondition( in reverseBranchCondition()
591 unsigned AArch64InstrInfo::removeBranch(MachineBasicBlock &MBB, in removeBranch()
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| H A D | AArch64.td | 37 include "AArch64InstrInfo.td"
43 def AArch64InstrInfo : InstrInfo;
175 let InstructionSet = AArch64InstrInfo;
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| H A D | AArch64BranchTargets.cpp | 135 const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( in addBTI()
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| H A D | AArch64Schedule.td | 13 const AArch64InstrInfo *TII =
14 static_cast<const AArch64InstrInfo*>(SchedModel->getInstrInfo());
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| H A D | AArch64LowerHomogeneousPrologEpilog.cpp | 44 const AArch64InstrInfo *TII;
217 AArch64InstrInfo::getMemOpInfo(Opc, Scale, Width, MinOffset, MaxOffset); in emitStore()
258 AArch64InstrInfo::getMemOpInfo(Opc, Scale, Width, MinOffset, MaxOffset); in emitLoad()
652 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| H A D | AArch64CondBrTuning.cpp | 48 const AArch64InstrInfo *TII;
293 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| H A D | AArch64Subtarget.h | 100 AArch64InstrInfo InstrInfo;
149 const AArch64InstrInfo *getInstrInfo() const override { return &InstrInfo; } in getInstrInfo()
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| H A D | AArch64FrameLowering.cpp | 309 ? AArch64InstrInfo::isTailCallReturnInst(*MBBI) in getArgumentStackToRestore()
602 const AArch64InstrInfo *TII = in eliminateCallFramePseudoInstr()
603 static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in eliminateCallFramePseudoInstr()
1044 } else if (AArch64InstrInfo::isFpOrNEON(Reg)) { in emitZeroCallUsedRegs()
1051 const AArch64InstrInfo &TII = *STI.getInstrInfo(); in emitZeroCallUsedRegs()
1560 bool Success = static_cast<const AArch64InstrInfo *>(TII)->getMemOpInfo( in convertCalleeSaveRestoreToSPPrePostIncDec()
1575 if (NeedsWinCFI && AArch64InstrInfo::isSEHInstruction(*MBBI)) in convertCalleeSaveRestoreToSPPrePostIncDec()
1589 if (AArch64InstrInfo::isSEHInstruction(*SEH)) in convertCalleeSaveRestoreToSPPrePostIncDec()
1632 if (AArch64InstrInfo::isSEHInstruction(MI)) in fixupCalleeSaveRestoreStackOffset()
1671 assert(AArch64InstrInfo::isSEHInstruction(*MBBI) && in fixupCalleeSaveRestoreStackOffset()
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| H A D | AArch64StackTaggingPreRA.cpp | 59 const AArch64InstrInfo *TII;
334 TII = static_cast<const AArch64InstrInfo *>(MF->getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| H A D | AArch64SchedPredicates.td | 78 "AArch64InstrInfo::isFpOrNEON"
84 "AArch64InstrInfo::isHForm"
90 "AArch64InstrInfo::isQForm"
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| H A D | AArch64StorePairSuppress.cpp | 32 const AArch64InstrInfo *TII;
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| H A D | AArch64PBQPRegAlloc.cpp | 141 assert(AArch64InstrInfo::isFpOrNEON(reg1) && in haveSameParity()
143 assert(AArch64InstrInfo::isFpOrNEON(reg2) && in haveSameParity()
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| H A D | AArch64InstrInfo.h | 176 class AArch64InstrInfo final : public AArch64GenInstrInfo {
181 explicit AArch64InstrInfo(const AArch64Subtarget &STI);
666 const AArch64InstrInfo *TII);
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| H A D | AArch64RegisterInfo.cpp | 891 const AArch64InstrInfo *TII = in materializeFrameBaseRegister()
919 const AArch64InstrInfo *TII = in resolveFrameIndex()
931 const AArch64InstrInfo *TII) { in createScratchRegisterForInstruction()
991 const AArch64InstrInfo *TII = in eliminateFrameIndex()
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| H A D | AArch64SIMDInstrOpt.cpp | 700 const AArch64InstrInfo *AAII = in runOnMachineFunction()
701 static_cast<const AArch64InstrInfo *>(ST.getInstrInfo()); in runOnMachineFunction()
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| H A D | AArch64PointerAuth.cpp | 39 const AArch64InstrInfo *TII = nullptr;
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| H A D | AArch64MIPeepholeOpt.cpp | 89 const AArch64InstrInfo *TII;
843 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| H A D | AArch64ExpandPseudoInsts.cpp | 49 const AArch64InstrInfo *TII;
794 const AArch64InstrInfo *TII, in createCallWithOps()
825 const AArch64InstrInfo *TII, in createCall()
1790 TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); in runOnMachineFunction()
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| H A D | AArch64FalkorHWPFFix.cpp | 197 const AArch64InstrInfo *TII;
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| H A D | AArch64AsmPrinter.cpp | 2778 assert(!AArch64InstrInfo::isTailCallReturnInst(*MI) && in emitInstruction()
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| /freebsd/lib/clang/libllvm/ |
| H A D | Makefile | 1387 SRCS_MIN+= Target/AArch64/AArch64InstrInfo.cpp
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 521 const AArch64InstrInfo &TII;
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